SPRZ193T January   2003  – December 2023 SM320F2812 , SM320F2812-EP , SMJ320F2812 , TMS320F2810 , TMS320F2810-Q1 , TMS320F2811 , TMS320F2811-Q1 , TMS320F2812 , TMS320F2812-Q1

 

  1.   1
  2. 1Introduction
  3. 2Device and Development Tool Support Nomenclature
  4. 3Device Markings
  5. 4Usage Notes and Known Design Exceptions to Functional Specifications
    1. 4.1 Usage Notes
      1. 4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
  6. 5Known Design Exceptions to Functional Specifications
    1.     Advisory
    2.     Advisory
    3.     Advisory
    4.     Advisory
    5.     Advisory
    6.     Advisory
    7.     Advisory
    8.     Advisory
    9.     Advisory
    10.     Advisory
    11.     Advisory
    12.     Advisory
    13.     Advisory
    14.     Advisory
    15.     Advisory
    16.     Advisory
    17.     Advisory
    18.     Advisory
    19.     Advisory
    20.     Advisory
    21.     Advisory
    22.     Advisory
    23.     Advisory
    24.     Advisory
    25.     Advisory
    26.     Advisory
    27.     Advisory
    28.     Advisory
    29.     Advisory
    30.     Advisory
    31.     Advisory
  7. 6Documentation Support
  8. 7Trademarks
  9. 8Revision History

Advisory

WD: WDFLAG Bit Does Not Work as Intended

Revision(s) Affected

0, A, B, C, D, E, F and G

Details

The WDFLAG bit in F281x devices cannot be used to reliably distinguish a watchdog-initiated reset from a power-on (or warm) reset. This is because the device expects the XRS pin to be pulled high (by the external reset circuit) within 4 SYSCLKOUT cycles (8 OSCLK cycles at power up) after the end of the watchdog-initiated reset pulse, which is 512 OSCCLK cycles. Most of the external XRS circuits cannot provide the fast rise time requirement (due to the capacitance); therefore, the WDFLAG bit should not be used in applications.

Workaround(s)

None. This bit should not be used.