SPRUJ63C September   2022  – February 2026

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 EVM Revisions and Assembly Variants
    5. 1.5 Specification
    6. 1.6 Functional Block Diagram
  7. 2Hardware
    1. 2.1 Additional Images
    2. 2.2 Power
      1. 2.2.1 Power-On/Off Procedures
      2. 2.2.2 Power-On Procedure
      3. 2.2.3 Power-Off Procedure
      4.      19
      5. 2.2.4 Power Input
      6. 2.2.5 Reverse Polarity Protection
      7. 2.2.6 Current Monitoring
      8. 2.2.7 Power Supply
      9. 2.2.8 Power Sequencing
      10. 2.2.9 AM64x/AM243x Power
    3. 2.3 Peripheral and Major Component Description
      1. 2.3.1  Configuration
        1. 2.3.1.1 Boot Modes
      2. 2.3.2  Clocking
        1. 2.3.2.1 Ethernet PHY Clock
        2. 2.3.2.2 AM64x/AM243x Clock
        3. 2.3.2.3 PCIe Clock
      3. 2.3.3  Reset
      4. 2.3.4  JTAG
      5. 2.3.5  Test Automation
      6. 2.3.6  UART Interfaces
      7. 2.3.7  Memory Interfaces
        1. 2.3.7.1 DDR4 Interface
        2. 2.3.7.2 MMC Interfaces
          1. 2.3.7.2.1 Micro SD Interface
          2. 2.3.7.2.2 eMMC Interface
        3. 2.3.7.3 OSPI Interface
        4. 2.3.7.4 SPI EEPROM Interface
        5. 2.3.7.5 Board ID EEPROM Interface
      8. 2.3.8  Ethernet Interface
        1. 2.3.8.1 DP83867 PHY Default Configuration
        2. 2.3.8.2 DP83869 PHY Default Configuration
        3. 2.3.8.3 Ethernet LED
      9. 2.3.9  Display Interface
      10. 2.3.10 USB 2.0 Interface
      11. 2.3.11 PCIe Interface
      12. 2.3.12 High Speed Expansion Interface
      13. 2.3.13 CAN Interface
      14. 2.3.14 Interrupt
      15. 2.3.15 ADC Interface
      16. 2.3.16 Safety Connector
      17. 2.3.17 SPI Interfaces
      18. 2.3.18 I2C Interfaces
      19. 2.3.19 FSI Interface
  8. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  9. 4Compliance Information
    1. 4.1 EMC, EMI, and ESD Compliance
  10. 5Additional Information
    1. 5.1 Known Issues and Modifications
      1. 5.1.1 Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS
      2. 5.1.2 Issue 2 - DC Barrel Jack Warning when Hot-Plugging
      3. 5.1.3 Issue 3 - uSD Card Boot Not Working
      4. 5.1.4 Issue 4 - Damage LM5140 after Hot Plug DC Jack
      5. 5.1.5 Issue 5 - CPTS0 PTP Jitter Issue
    2.     Trademarks
  11. 6Related Documentation
  12. 7References
  13. 8Revision History

1.5 Specification

AM64x System-on-Chip (SoC):

  • AM64x combines two instances of Sitara’s gigabit TSN-enabled PRU-ICSSG with up to two Arm® Cortex®-A53 cores, up to four Cortex-R5F MCUs, and a single Cortex-M4F MCU

AM243x Microcontroller (MCU):

  • AM243x combines two instances of Sitara’s gigabit TSN-enabled PRU-ICSSG with up to two Cortex-R5F MCU, and a single Cortex-M4F MCU

Memory

  • 2GB DDR4 supporting data rate up to 1600MT/s
  • 16GB eMMC Flash which can support HS400 speed of operation
  • Micro Secure Digital (SD) Card with UHS-1 support
  • 1 Kbit Serial Peripheral Interface (SPI) EEPROM
  • 512 Mbit OSPI EEPROM
  • Mbit Inter-Integrated Circuit (I2C) Boot EEPROM

I/O Interface:

  • One CPSW Gigabit Ethernet port and two Industrial Ethernet ports based on the Gigabit Industrial Communication Subsystem (PRU-ICSS-Gb) paired with Texas Instruments Gigabit Ethernet PHY
  • One USB2.0 interface with Micro AB connector

Expansion Bus:

  • 10051922-1410ELF - 14-Pin FPC connector to interface with the OSD9616P0992-10 display
  • High Speed Expansion (HSE) connector to connect application cards
  • 2x5 header - 67997-410HLF FSI connector to connect with the C2000 EVM
  • x4 PCIe connector to support 1 lane PCIe Card

Debug:

  • XDS110 On-Board Emulator
  • Supports 20-pin JTAG connection from external emulator
  • Automatic selection between on-board and external emulator (higher priority)
  • Quad port Universal Asynchronous Receiver/Transmitter (UART) to USB circuit over microB USB connector
  • Two I2C ports SoC_I2C0 and SoC_I2C1 connected to test headers for peripheral testing of the AM64x device
  • 4x Push Buttons:
    • 1x SoC Warm RESET
    • 1x User GPIO
    • 1x MCU Warm RESET
    • 1x MCU/SoC PORz RESET

Compliance:

  • RoHS Compliant
  • REACH Compliant