SPRUJ63C September   2022  – February 2026

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 EVM Revisions and Assembly Variants
    5. 1.5 Specification
    6. 1.6 Functional Block Diagram
  7. 2Hardware
    1. 2.1 Additional Images
    2. 2.2 Power
      1. 2.2.1 Power-On/Off Procedures
      2. 2.2.2 Power-On Procedure
      3. 2.2.3 Power-Off Procedure
      4.      19
      5. 2.2.4 Power Input
      6. 2.2.5 Reverse Polarity Protection
      7. 2.2.6 Current Monitoring
      8. 2.2.7 Power Supply
      9. 2.2.8 Power Sequencing
      10. 2.2.9 AM64x/AM243x Power
    3. 2.3 Peripheral and Major Component Description
      1. 2.3.1  Configuration
        1. 2.3.1.1 Boot Modes
      2. 2.3.2  Clocking
        1. 2.3.2.1 Ethernet PHY Clock
        2. 2.3.2.2 AM64x/AM243x Clock
        3. 2.3.2.3 PCIe Clock
      3. 2.3.3  Reset
      4. 2.3.4  JTAG
      5. 2.3.5  Test Automation
      6. 2.3.6  UART Interfaces
      7. 2.3.7  Memory Interfaces
        1. 2.3.7.1 DDR4 Interface
        2. 2.3.7.2 MMC Interfaces
          1. 2.3.7.2.1 Micro SD Interface
          2. 2.3.7.2.2 eMMC Interface
        3. 2.3.7.3 OSPI Interface
        4. 2.3.7.4 SPI EEPROM Interface
        5. 2.3.7.5 Board ID EEPROM Interface
      8. 2.3.8  Ethernet Interface
        1. 2.3.8.1 DP83867 PHY Default Configuration
        2. 2.3.8.2 DP83869 PHY Default Configuration
        3. 2.3.8.3 Ethernet LED
      9. 2.3.9  Display Interface
      10. 2.3.10 USB 2.0 Interface
      11. 2.3.11 PCIe Interface
      12. 2.3.12 High Speed Expansion Interface
      13. 2.3.13 CAN Interface
      14. 2.3.14 Interrupt
      15. 2.3.15 ADC Interface
      16. 2.3.16 Safety Connector
      17. 2.3.17 SPI Interfaces
      18. 2.3.18 I2C Interfaces
      19. 2.3.19 FSI Interface
  8. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  9. 4Compliance Information
    1. 4.1 EMC, EMI, and ESD Compliance
  10. 5Additional Information
    1. 5.1 Known Issues and Modifications
      1. 5.1.1 Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS
      2. 5.1.2 Issue 2 - DC Barrel Jack Warning when Hot-Plugging
      3. 5.1.3 Issue 3 - uSD Card Boot Not Working
      4. 5.1.4 Issue 4 - Damage LM5140 after Hot Plug DC Jack
      5. 5.1.5 Issue 5 - CPTS0 PTP Jitter Issue
    2.     Trademarks
  11. 6Related Documentation
  12. 7References
  13. 8Revision History

2.3.7.3 OSPI Interface

The EVM has 512 Mbit OSPI memory device of part number S28HS512TGABHM010 from Cypress is connected to OSPI0 interface of AM64x/AM243x SoC. The OSPI supports single and double data rates with memory speed up to 200MBps SDR and 400MBps DDR (200 MHz clock speed).

Two signals are routed to OSPI0_DQS:

  1. OSPI0_DQS from the memory device.
  2. OSPI0_LBCLK from SoC.

To route DQS from memory device, Mount R601 and R592 and DNI R600 and R591.

To route OSPI0_LBCLK from SoC, Mount R600 and R591 and DNI R601 and R592

Note: For more information, see the OSPI and QSPI Board Design and Layout Guidelines section in the AM64x Sitara™ Processors Data Manual.

OSPI and QSPI implementation: 0 Ω resistors are provided for DATA[7:0], DQS, INT# and CLK signals. Footprints to mount external pull up resistors are provided on DATA[7:0] to prevent bus floating. The footprint for the OSPI memory also allows the installation of either a QSPI memory or an OSPI memory. S25FL256SABHI200 from Cypress is used in variants where QSPI flash is required. The 0 ohm resistors used in pins OSPI_DATA[4:7] are removed if QSPI flash is mounted.

Note: For QSPI Configuration

Remove 0E resistors from the following

  1. OSPI_DQ4 to OSPI_DQ7 nets (R432, R441, R442, R443).
  2. OSPI_INTn (R158).

TMDS243EVM TMDS64EVM AM64x/AM243x OSPI InterfaceFigure 2-18 AM64x/AM243x OSPI Interface