SPRUJ63C September   2022  – February 2026

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 EVM Revisions and Assembly Variants
    5. 1.5 Specification
    6. 1.6 Functional Block Diagram
  7. 2Hardware
    1. 2.1 Additional Images
    2. 2.2 Power
      1. 2.2.1 Power-On/Off Procedures
      2. 2.2.2 Power-On Procedure
      3. 2.2.3 Power-Off Procedure
      4.      19
      5. 2.2.4 Power Input
      6. 2.2.5 Reverse Polarity Protection
      7. 2.2.6 Current Monitoring
      8. 2.2.7 Power Supply
      9. 2.2.8 Power Sequencing
      10. 2.2.9 AM64x/AM243x Power
    3. 2.3 Peripheral and Major Component Description
      1. 2.3.1  Configuration
        1. 2.3.1.1 Boot Modes
      2. 2.3.2  Clocking
        1. 2.3.2.1 Ethernet PHY Clock
        2. 2.3.2.2 AM64x/AM243x Clock
        3. 2.3.2.3 PCIe Clock
      3. 2.3.3  Reset
      4. 2.3.4  JTAG
      5. 2.3.5  Test Automation
      6. 2.3.6  UART Interfaces
      7. 2.3.7  Memory Interfaces
        1. 2.3.7.1 DDR4 Interface
        2. 2.3.7.2 MMC Interfaces
          1. 2.3.7.2.1 Micro SD Interface
          2. 2.3.7.2.2 eMMC Interface
        3. 2.3.7.3 OSPI Interface
        4. 2.3.7.4 SPI EEPROM Interface
        5. 2.3.7.5 Board ID EEPROM Interface
      8. 2.3.8  Ethernet Interface
        1. 2.3.8.1 DP83867 PHY Default Configuration
        2. 2.3.8.2 DP83869 PHY Default Configuration
        3. 2.3.8.3 Ethernet LED
      9. 2.3.9  Display Interface
      10. 2.3.10 USB 2.0 Interface
      11. 2.3.11 PCIe Interface
      12. 2.3.12 High Speed Expansion Interface
      13. 2.3.13 CAN Interface
      14. 2.3.14 Interrupt
      15. 2.3.15 ADC Interface
      16. 2.3.16 Safety Connector
      17. 2.3.17 SPI Interfaces
      18. 2.3.18 I2C Interfaces
      19. 2.3.19 FSI Interface
  8. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  9. 4Compliance Information
    1. 4.1 EMC, EMI, and ESD Compliance
  10. 5Additional Information
    1. 5.1 Known Issues and Modifications
      1. 5.1.1 Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS
      2. 5.1.2 Issue 2 - DC Barrel Jack Warning when Hot-Plugging
      3. 5.1.3 Issue 3 - uSD Card Boot Not Working
      4. 5.1.4 Issue 4 - Damage LM5140 after Hot Plug DC Jack
      5. 5.1.5 Issue 5 - CPTS0 PTP Jitter Issue
    2.     Trademarks
  11. 6Related Documentation
  12. 7References
  13. 8Revision History

2.2.9 AM64x/AM243x Power

The Core voltage of the AM64x/AM243x can be powered by 0.75 V or 0.8 V or 0.85 V based on the power optimization requirement. TI recommends to use a single voltage source when the SoC Core voltage (VDD_CORE) and SoC Array Core Voltage (VDDR_CORE) and other array core voltages (VDDA_0P85_SERDES0_C, VDDA_0P85_SERDES0, VDDA_0P85_USB0, VDD_DLL_MMC0, VDD_MMC0) is 0.85 V. In cases where the SoC Core voltage is required to be 0.75 V or 0.8 V and SoC Array Core Voltage and other Array Core voltages is required to be 0.85 V, there needs to be separate voltage supply for the SoC Core voltage and an separate supply for the SoC Array Core voltages.

This EVM has a provision for providing single voltage supply or different voltage supply to the SoC Core and SoC Array Core and other Array Core Voltages and based requirement. This can be configured by the placement of resistors as mentioned in Figure 2-7.

TMDS243EVM TMDS64EVM AM64x/AM243x Core Supply and Array Core Supply OptionsFigure 2-7 AM64x/AM243x Core Supply and Array Core Supply Options
Note:
  • PROC101x-001 BOM variant, implements the AM6442 and requires 0.75 V supplied to the VDD_CORE and 0.85 V supplied to VDDR_CORE. In this variant R2 and R4 are installed by default and VDD_CORE supply (U25) is setup for 0.75 V operation.
  • PROC101x-002 BOM variant, implements the AM2434 and requires 0.85 V supplied to VDD_CORE and VDDR_CORE. In this variant R1 and R3 are installed by default and VDD_CORE supply (U25) is setup for 0.85 V operation.

The SoC has different IO groups. Each IO group is powered by specific power supplies as shown in Table 2-7.

Table 2-7 SoC Power Supply
SI.No.Power SupplySoC Supply RailsIO Power GroupPower
1VDDA_COREVDDA_0P85_SERDES0SERDES00.85
VDDA_0P85_SERDES0_C0.85
VDDA_0P85_USB0USB00.85
VDD_MMC0MMC00.85
2SoC_DVDD3V3VDDS_MCUMCU3.3
VDDA_3P3_USB0USB03.3
VDDSHV0General3.3
VDDSHV1PRG03.3
VDDSHV2PRG13.3
VDDSHV3GPMC3.3
3VDDA_1V8_MCUVDDA_MCUMCU1.8
4VDDA_MCU_ADCVDDA_ADCADC01.8
5VDDA_1V8_SERDESVDDA_1P8_SERDES0SERDES01.8
6VDDA_1V8_USB0VDDA_1P8_USB0USB01.8
7VDDA_1V8VDDS_OSCOSC01.8
VDDA_TEMP_0/11.8
VDDA_PLL_0/1/21.8
8VDD_DDR4VDDS_DDRDDR01.2
VDDS_DDR_C1.2
9SOC_DVDD1V8VDDSHV4FLASH1.8
VDDS_MMC0MMC01.8
10VDDSHV_SD_IOVDDSHV5MMC13.3/1.8