SPRUJ51A June   2023  – November 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 EVM Revisions and Assembly Variants
    5. 1.5 Specification
  6. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Key Features
      1. 2.2.1 Processor
      2. 2.2.2 Memory
      3. 2.2.3 JTAG Emulator
      4. 2.2.4 Supported Interfaces and Peripherals
      5. 2.2.5 Expansion Connectors Headers to Support Application Specific Add On Boards
    3. 2.3  Power
      1. 2.3.1 Power Requirements
      2. 2.3.2 Power Input
      3. 2.3.3 Power Supply
      4. 2.3.4 Power ON OFF Procedures
        1. 2.3.4.1 Power-On Procedure
        2. 2.3.4.2 Power-Off Procedure
        3. 2.3.4.3 Power Test Points
      5. 2.3.5 Power Sequencing
      6. 2.3.6 AM62x 17x17 SoC Power
      7. 2.3.7 Current Monitoring
    4. 2.4  AM62x-Low Power SK EVM Interface Mapping
    5. 2.5  Clocking
    6. 2.6  Reset
    7. 2.7  OLDI Display Interface
    8. 2.8  CSI Interface
    9. 2.9  Audio Codec Interface
    10. 2.10 HDMI Display Interface
    11. 2.11 JTAG Interface
    12. 2.12 Test Automation Header
    13. 2.13 UART Interface
    14. 2.14 USB Interface
      1. 2.14.1 USB2.0 Type A Interface
      2. 2.14.2 USB2.0 Type C Interface
    15. 2.15 Memory Interfaces
      1. 2.15.1 LPDDR4 Interface
      2. 2.15.2 OSPI
      3. 2.15.3 MMC Interfaces
        1. 2.15.3.1 MMC0 - eMMC Interface
        2. 2.15.3.2 MMC1 - Micro SD Interface
        3. 2.15.3.3 MMC2 - M2 Key E Interface
      4. 2.15.4 EEPROM
    16. 2.16 Ethernet Interface
      1. 2.16.1 CPSW Ethernet PHY1 Default Configuration
      2. 2.16.2 CPSW Ethernet PHY2 Default Configuration
    17. 2.17 GPIO Port Expander
    18. 2.18 GPIO Mapping
    19. 2.19 AM62x-Low Power SK EVM User Setup and Configuration
      1. 2.19.1 EVM DIP Switches
      2. 2.19.2 Boot Modes
      3. 2.19.3 User Test LEDs
    20. 2.20 Expansion Headers
      1. 2.20.1 User Expansion Connector
      2. 2.20.2 MCU Connector
      3. 2.20.3 PRU Connector
    21. 2.21 Push Buttons
    22. 2.22 I2C Address Mapping
  7. 3Hardware Design Files
  8. 4Compliance Information
    1. 4.1 EMC, EMI and ESD Compliance
  9. 5Additional Information
    1. 5.1 Known Issues and Modifications
    2.     Trademarks
    3.     72
  10. 6Revision History

2.8 CSI Interface

The CSI-2 interface from the AM62x 17x17 SoC is terminated to a 40 pin Camera MIPI connector QSH-020-01-L-D-DP-A-K. The SoC supports 4 CSI RX Lanes, four are pinned out on the SKEVM. The table below contains 40 pin Camera MIPI connector pin-out. SoC I2C2 signals are also connected to the CSI Header. IO Expander GPIO signals are connected to the camera GPIO’s.
CSI Interface Block Diagram Figure 2-10 CSI Interface Block Diagram
Table 2-9 CSI Camera Connector J19 Pinout
Pin No Pin Description Pin No Pin Description
1 NC 21 CSI0_RXP3
2 CSI_I2C2_SCL_BUFF 22 CSI_GPIO4_buff
3 NC 23 CSI0_RXN3
4 CSI_I2C2_SDA_BUFF 24 Ground
5 CSI0_RXCLKP 25 NC
6 CSI_GPIO0_buff 26 NC
7 CSI0_RXCLKN 27 NC
8 CSI_GPIO1_buff 28 NC
9 CSI0_RXP0 29 NC
10 CSI_REFCLK 30 VCC_3V3_SYS
11 CSI0_RXN0 31 NC
12 Ground 32 VCC_3V3_SYS
13 CSI0_RXP1 33 NC
14 CSI_RSTz_buff 34 VCC_3V3_SYS
15 CSI0_RXN1 35 NC
16 Ground 36 VCC_3V3_SYS
17 CSI0_RXP2 37 NC
18 CSI_GPIO2_buff 38 VCC_CSI_IO
19 CSI0_RXN2 39 NC
20 CSI_GPIO3_buff 40 VCC_CSI_IO