SPRUJ51A June   2023  – November 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 EVM Revisions and Assembly Variants
    5. 1.5 Specification
  6. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Key Features
      1. 2.2.1 Processor
      2. 2.2.2 Memory
      3. 2.2.3 JTAG Emulator
      4. 2.2.4 Supported Interfaces and Peripherals
      5. 2.2.5 Expansion Connectors Headers to Support Application Specific Add On Boards
    3. 2.3  Power
      1. 2.3.1 Power Requirements
      2. 2.3.2 Power Input
      3. 2.3.3 Power Supply
      4. 2.3.4 Power ON OFF Procedures
        1. 2.3.4.1 Power-On Procedure
        2. 2.3.4.2 Power-Off Procedure
        3. 2.3.4.3 Power Test Points
      5. 2.3.5 Power Sequencing
      6. 2.3.6 AM62x 17x17 SoC Power
      7. 2.3.7 Current Monitoring
    4. 2.4  AM62x-Low Power SK EVM Interface Mapping
    5. 2.5  Clocking
    6. 2.6  Reset
    7. 2.7  OLDI Display Interface
    8. 2.8  CSI Interface
    9. 2.9  Audio Codec Interface
    10. 2.10 HDMI Display Interface
    11. 2.11 JTAG Interface
    12. 2.12 Test Automation Header
    13. 2.13 UART Interface
    14. 2.14 USB Interface
      1. 2.14.1 USB2.0 Type A Interface
      2. 2.14.2 USB2.0 Type C Interface
    15. 2.15 Memory Interfaces
      1. 2.15.1 LPDDR4 Interface
      2. 2.15.2 OSPI
      3. 2.15.3 MMC Interfaces
        1. 2.15.3.1 MMC0 - eMMC Interface
        2. 2.15.3.2 MMC1 - Micro SD Interface
        3. 2.15.3.3 MMC2 - M2 Key E Interface
      4. 2.15.4 EEPROM
    16. 2.16 Ethernet Interface
      1. 2.16.1 CPSW Ethernet PHY1 Default Configuration
      2. 2.16.2 CPSW Ethernet PHY2 Default Configuration
    17. 2.17 GPIO Port Expander
    18. 2.18 GPIO Mapping
    19. 2.19 AM62x-Low Power SK EVM User Setup and Configuration
      1. 2.19.1 EVM DIP Switches
      2. 2.19.2 Boot Modes
      3. 2.19.3 User Test LEDs
    20. 2.20 Expansion Headers
      1. 2.20.1 User Expansion Connector
      2. 2.20.2 MCU Connector
      3. 2.20.3 PRU Connector
    21. 2.21 Push Buttons
    22. 2.22 I2C Address Mapping
  7. 3Hardware Design Files
  8. 4Compliance Information
    1. 4.1 EMC, EMI and ESD Compliance
  9. 5Additional Information
    1. 5.1 Known Issues and Modifications
    2.     Trademarks
    3.     72
  10. 6Revision History

2.7 OLDI Display Interface

The OLDI0 Display interface of the AM62x 17x17 SoC is connected to 40 pin LVDS display connector (J22) Mfr Part # FFC2A32-40-T from GCT. The OLDI Interface supports dual channel 8 bit LVDS output. The Pin-out details of the Display connector/ are given in Table 2-8.

OLDI Interface Block Diagram Figure 2-9 OLDI Interface Block Diagram
Table 2-8 Display Connector Pinout
Pin no. Signal Pin no. Signal
1 VCC_3V3_SYS(EEPROM_VDD) 21 CH1_LVDS_A2P
2 SoC_I2C0_SCL 22 GND
3 SoC_I2C0_SDA 23 CH1_LVDS_A3N
4 NC 24 CH1_LVDS_A3P
5 NC 25 GND
6 GND 26 CH2_LVDS_A0N
7 GND 27 CH2_LVDS_A0P
8 OLDI_RESETn 28 GND
9 GPIO_OLDI_INT 29 CH2_LVDS_A1N
10 GND 30 CH2_LVDS_A1P
11 CH1_LVDS_A0N 31 GND
12 CH1_LVDS_A0P 32 CH2_LVDS_CLKN
13 GND 33 CH2_LVDS_CLKP
14 CH1_LVDS_A1N 34 GND
15 CH1_LVDS_A1P 35 CH2_LVDS_A2N
16 GND 36 CH2_LVDS_A2P
17 CH1_LVDS_CLKN 37 GND
18 CH1_LVDS_CLKP 38 CH2_LVDS_A3N
19 GND 39 CH2_LVDS_A3P
20 CH1_LVDS_A2N 40 GND