SPRUIM6A October   2018  – November 2020

 

  1. 1Introduction
    1. 1.1 Key Features
  2. 2AM65x IDK Overview
  3. 3Common Processor Board
    1. 3.1 Key Features
    2. 3.2 Functional Block Diagram
    3. 3.3 Overview of Common Processor Board
      1. 3.3.1  Clocking
        1. 3.3.1.1 RTC Clock
        2. 3.3.1.2 Maxwell SoC Clock
        3. 3.3.1.3 Ethernet PHY Clocks
        4. 3.3.1.4 SERDES Clock
      2. 3.3.2  Reset
      3. 3.3.3  Power Requirements
        1. 3.3.3.1 Power Input
        2. 3.3.3.2 Overvoltage and Undervoltage Protection Circuit
        3. 3.3.3.3 Voltage Supervisor
        4. 3.3.3.4 Current Monitoring
        5. 3.3.3.5 Power Supply
        6. 3.3.3.6 Power Sequencing
        7. 3.3.3.7 SoC Power
      4. 3.3.4  Configuration
        1. 3.3.4.1 Boot Modes
        2. 3.3.4.2 JTAG
          1. 3.3.4.2.1 Test Automation
        3. 3.3.4.3 UART Interface
      5. 3.3.5  Memory Interfaces
        1. 3.3.5.1 DDR4 Interface
        2. 3.3.5.2 MMC Interface
          1. 3.3.5.2.1 SDHC Interface
          2. 3.3.5.2.2 eMMC Interface
        3. 3.3.5.3 OSPI Interface
        4. 3.3.5.4 SPI NOR Flash Interface
        5. 3.3.5.5 Board ID EEPROM Interface
        6. 3.3.5.6 Boot EEPROM Interface
      6. 3.3.6  Ethernet Interface
        1. 3.3.6.1 Gigabit Ethernet PHY Default Configuration
        2. 3.3.6.2 Ethernet LEDs
      7. 3.3.7  LCD Display Interface
      8. 3.3.8  USB 2.0 Interface
      9. 3.3.9  CSI-2 Interface
      10. 3.3.10 Application Card Interface
      11. 3.3.11 SERDES Interface
      12. 3.3.12 GPMC/DSS Interface
      13. 3.3.13 I2C Interface
      14. 3.3.14 SPI Interface
      15. 3.3.15 Timer and Interrupt
        1. 3.3.15.1 Timer
        2. 3.3.15.2 Interrupt
      16. 3.3.16 Fan Connector
  4. 4IDK Application Card
    1. 4.1 Key Features
    2. 4.2 Overview of IDK Application Board
      1. 4.2.1 Application Card Connector
      2. 4.2.2 Profibus Interface
      3. 4.2.3 CAN Interface
      4. 4.2.4 Rotary Switch
      5. 4.2.5 Industrial I/O Terminal Connector
      6. 4.2.6 Ethernet Interface
      7. 4.2.7 Board ID Memory
      8. 4.2.8 Power Supply
  5. 5x2 Lane PCIe Personality Card
    1. 5.1 Key Features
    2. 5.2 Overview of PCIex2 Daughter Card
      1. 5.2.1 Personality Card Connectors
      2. 5.2.2 USB 2.0 Interface
      3. 5.2.3 PCIe Interface
      4. 5.2.4 x2 Lane PCIe Personality Card Clocking
      5. 5.2.5 Board ID EEPROM Interface
      6. 5.2.6 x2 Lane PCIe Personality Card Power
  6. 6Known Issues
    1. 6.1 Determining the Revision and Date Code for the EVM
    2. 6.2 Known Issues for the A, E4, and E3 Revision
      1. 6.2.1 Lack of Reset for I2C IO Expander
    3. 6.3 Known Issues for the E4 & E3 Revision
      1. 6.3.1 Changes Unique to the E4 Revision Modified for 2.0 Revision
    4. 6.4 Known Issues for the E3 Revision
      1. 6.4.1 Resonance Observed on the SoC Side of Some Filters Associated with VDDA_1V8
      2. 6.4.2 Additional LDO Power Supply Needed for VDDA_1P8_SERDES0
      3. 6.4.3 Length of the RESET Signal to the PCIE Connectors on the SERDES Daughter Card
      4. 6.4.4 The PORz_OUT and MCU_PORz_OUT Signals Go High During Power Sequencing
      5. 6.4.5 Orientation of the Current Monitoring Shunt Resistors
      6. 6.4.6 SD Card IO Supply Capacitance
      7. 6.4.7 PHY Resistor Strapping Changed to Disable EEE Mode
      8. 6.4.8 The I2C Address for the I2C Boot Memory changed to 0x52
  7. 7Configuring the PRG0 and PRG1 Ethernet Interface to MII
    1. 7.1 Ethernet PHY Initial Conditions and TX Clock Signal Change
      1. 7.1.1 Ethernet PHY0 Clock and Initial Condition for MII
      2. 7.1.2 Ethernet PHY1 Clock and Initial Condition for MII
      3. 7.1.3 Ethernet PHY2 Clock and Initial Condition for MII
      4. 7.1.4 Ethernet PHY3 Clock and Initial Condition for MII
    2. 7.2 Ethernet PHY and TX Data Signals Change
      1. 7.2.1 Ethernet PHY0 TX Data Signals for MII
      2. 7.2.2 Ethernet PHY1 TX Data Signals for MII
      3. 7.2.3 Ethernet PHY2 TX Data Signals for MII
      4. 7.2.4 Ethernet PHY3 TX Data Signals for MII
  8. 8Revision History

3.3.4.1 Boot Modes

The boot mode for the SoC is defined by a bank of switches SW2, SW3, and SW4. Switch set to “ON” corresponds to logic “HIGH”, while “OFF” corresponds to logic “LOW”. The following boot modes are supported:

  1. No boot
  2. OSPI
  3. MMC1 - SDCard
  4. MMC 0- eMMC installed
  5. PCIE - PCIE as an endpoint
  6. CPSW - Ethernet slave boot
  7. USB - boot using host mode with bulk storage. USB2.0 mass storage device using FAT16/32 (such as a thumb drive)
  8. USB - device boot DFU
  9. UART
  10. I2C EEPROM

The BOOTMODE pins provide the means to select the boot mode before the device is powered up. They are divided into the following categories.

GUID-6AADB59A-DBE5-415F-B7A1-976026E4F276-low.jpgFigure 3-8 BOOTMODE Bits

BOOTMODE[3:0] – This provides the primary boot mode configuration to select the requested boot mode after POR; that is, the peripheral/memory to boot from.

Table 3-8 Boot Device Selection BOOTMODE[3:0]
SW3.4SW3.3SW3.2SW3.1Primary Boot Device Selected
offoffoffoffSleep (No boot – debug mode)
offoffoffonOSPI
offoffonoffQSPI
offoffononHyperflash
offonoffoffSPI (on QSPI/OSPI port 0 in legacy SPI mode)
offonoffonI2C
offononoffMMC/SD card, eMMC boot from UDA or file system
offonononEthernet
onoffoffoffUSB
onoffoffonPCIe
onoffonoffUART
onoffononReserved
ononoffoffGPMC XIP
ononoffoneMMC boot from boot partition (with auto-fall back to file system)
onononoffReserved (acts as no boot)
ononononReserved (acts as no boot)

BOOTMODE[6:4] – Select the backup boot mode; that is, the peripheral/memory to boot from, if the primary boot device failed.

Table 3-9 Backup Boot Mode Selection BOOTMODE[6:4]
SW3.7SW3.6SW3.5Backup Boot Device Selected
offoffoffNone (No backup mode)
offoffonUSB
offonoffUART
offononEthernet
onoffoffMMC/SD
onoffonSPI on OSPI/OSPI port 0 in legacy SPI mode)
ononoffHyper flash
onononI2C

BOOTMODE07 – This is the minimum (MIN) configuration pin. The min pin is provided as a way to use minimal pin strapping to configure boot. When the min pin value is 1, all configuration fields are based on pre-defined default values. In this case, no boot mode pins beyond the min pin need to be driven because their values are ignored.

BOOTMODE[15:8] – These pins provide optional settings and are used in conjunction with the primary boot device selected. Refer to the AM65x Multicore ARM Keystone III System-on-Chip (SoC) Technical Reference Manual for more details.

Table 3-10 Primary Boot Media Configuration BOOTMODE[15:8]
SW2.6SW2.5SW2.4SW2.3SW2.2SW2.1SW3.10SW3.9Boot Device
Not UsedSleep
Pin CmdCselSpeedAdr WidOSPI
PortPin CmdCselSpeedAdr WidQSPI
Not UsedCselSpeedHyperflash
PortModeCselCmdAdr WidthSPI
Not UsedBus ResetModeSpdAddrI2C
Not UsedPortInterface Config1bitMMC/SD card
clkoutifacespddplxExtern conEthernet
Not UsedUsb3ModePortUSB
PortDualsrefBAR Config PCIe
Not UsedUART
IdxAD muxCsel SizeCselWidGPMC XIP
Not UsedPortAltBus WidthSpeedackeMMC

BOOTMODE[18:16] – These pins provide optional settings and are used in conjunction with the backup boot device devices. Refer to the AM65x Multicore ARM Keystone III System-on-Chip (SoC) Technical Reference Manual for more information on bit details. Switches SW2.[7:9] when on sets 1 and sets 0 if off.

Table 3-11 Backup Boot Media Configuration BOOTMODE[18:16]
SW2.9SW2.8SW2.7Boot Device
Not UsedNone
Not UsedPortUSB
Not UsedUART
clkoutInterfaceEthernet
Not UsedPort1 BitMMC/SD
PortAdr Width/CmdSPI
SpeedHyperflash
resetModeAddrI2C

MCU_BOOTMODE pins provide ROM code with information for the system clock speed and fail-safe boot device.

Table 3-12 MCU BOOTMODE Bits
Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
ReservedFail Safe modeRef Clock Select

MCU_BOOTMODE[2:0] – Denotes system clock frequency for PLL configuration. By default, these bits are set for 25 MHz.

Table 3-13 PLL Reference Clock Selection MCU_BOOTMODE[2:0]
Bit 2Bit 1Bit 0PLL REF CLK (MHz)
00019.2
00120
01024
01125
10026
10127
110Reserved
111No PLL Configuration Done (slow speed backup)

MCU_BOOTMODE[4:3] – Select the fail-safe boot mode, as shown in Table 3-14.

Table 3-14 Fail-Safe Boot Configuration
SW4.2SW4.1PLL REF CLK (MHz)
offoffNo fail-safe boot supported
offonI2C port 0
onoffSPI Port 0
ononHyperflash Port 0

MCU_BOOTMODE[10:5]- Reserved

GUID-3F4ADC18-D312-4681-BE08-EBF27BA4CB8B-low.pngFigure 3-9 BOOT Switches Provided on the Processor Card