SPMU378 April   2026 TPS26750A

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documents
    5.     Support Resources
    6.     Trademarks
  3. 1Introduction
    1. 1.1 Introduction
      1. 1.1.1 Purpose and Scope
    2. 1.2 PD Controller Host Interface Description
      1. 1.2.1 Overview
      2. 1.2.2 Register and field notation
    3. 1.3 Unique Address Interface
      1. 1.3.1 Unique Address Interface Protocol
  4. 2PD Controller Policy Modes
    1. 2.1 Overview
    2. 2.2 Source Policy Mode
    3. 2.3 Sink Policy Mode
  5. 3Register Overview
    1. 3.1 TPS26750A Registers
  6. 44CC Task Detailed Descriptions
    1. 4.1 Overview
    2. 4.2 CPU Control Tasks
      1. 4.2.1 'Gaid' - Return to normal operation
      2. 4.2.2 'GAID' - Cold reset request
    3. 4.3 PD Message Tasks
      1. 4.3.1  'SWSk' - PD PR_Swap to Sink
      2. 4.3.2  'SWSr' - PD PR_Swap to Source
      3. 4.3.3  'SWDF' - PD DR_Swap to DFP
      4. 4.3.4  'SWUF' - PD DR_Swap to UFP
      5. 4.3.5  'GSkC' - PD Get Sink Capabilities
      6. 4.3.6  'GSrC' - PD Get Source Capabilities
      7. 4.3.7  'ESkC' - PD EPR Get Sink Capabilities
      8. 4.3.8  'ESrC' - PD EPR Get Source Capabilities
      9. 4.3.9  'SSrC' - PD Send Source Capabilities
      10. 4.3.10 'GPPI' - PD Get Port Partner Information
      11. 4.3.11 'MBRd' - Message Buffer Read
    4. 4.4 Patch Bundle Update Tasks
      1. 4.4.1  'PBMs' - Start Patch Burst Mode Download Sequence
      2. 4.4.2  'PBMc' - Patch Burst Mode Download Complete
      3. 4.4.3  'PBMe' - End Patch Burst Mode Download Sequence
      4. 4.4.4  'GO2P' - Go to Patch Mode
      5. 4.4.5  'PTCs' - Start Patch Download Sequence
      6. 4.4.6  'PTCd' - Patch Download
      7. 4.4.7  'PTCc' - Patch Download Complete
      8. 4.4.8  'PTCq' - Patch Query
      9. 4.4.9  'PTCr' - Patch Reset
      10. 4.4.10 'FLrd' - Flash Memory Read
      11. 4.4.11 'FLad' - Flash Memory Write Start Address
      12. 4.4.12 'FLwd' - Flash Memory Write
      13. 4.4.13 'FLvy' - Flash Memory Verify
    5. 4.5 System Tasks
      1. 4.5.1 'ANeg' - Auto Negotiate Sink Update
      2. 4.5.2 'DBfg' - Clear Dead Battery Flag
      3. 4.5.3 'I2Cr' - I2C read transaction
      4. 4.5.4 'I2Cw' - I2C write transaction
      5. 4.5.5 'GPsh' - set GPIO high
      6. 4.5.6 'GPsl' - set GPIO low
  7. 5User Reference
    1. 5.1 PD Controller Application Customization
    2. 5.2 Loading a Patch Bundle
    3. 5.3 AUTO_NEGOTIATE_SINK Register
      1. 5.3.1 AUTO_NEGOTIATE_SINK Usage Example 1
      2. 5.3.2 AUTO_NEGOTIATE_SINK Usage Example 2
      3. 5.3.3 AUTO_NEGOTIATE_SINK Usage Example 3
      4. 5.3.4 AUTO_NEGOTIATE_SINK Usage Example 4
    4. 5.4 Liquid Detection Registers
    5. 5.5 GPIO Events
  8. 6Revision History

4.4.13 'FLvy' - Flash Memory Verify

Table 4-27 'FLvy' - External EEPROM Verify
DescriptionThe 'FLvy' Task verifies if the patch/configuration is valid.
INPUT DATAXBitNameDescription
31:0Flash AddressFlash Address
OUTPUT DATAXBitNameDescription
7:0ReturnCode
0x00hThe patch/configuration is valid.
0x01hThe patch/configuration is not valid.
Task CompletionThe 'FLvy' Task completes after header is checked and validated.
Side EffectsThe PD controller ignores the I2Cc_IRQ pin until this Task is completed.
Additional InformationNone