SPMU378 April   2026 TPS26750A

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documents
    5.     Support Resources
    6.     Trademarks
  3. 1Introduction
    1. 1.1 Introduction
      1. 1.1.1 Purpose and Scope
    2. 1.2 PD Controller Host Interface Description
      1. 1.2.1 Overview
      2. 1.2.2 Register and field notation
    3. 1.3 Unique Address Interface
      1. 1.3.1 Unique Address Interface Protocol
  4. 2PD Controller Policy Modes
    1. 2.1 Overview
    2. 2.2 Source Policy Mode
    3. 2.3 Sink Policy Mode
  5. 3Register Overview
    1. 3.1 TPS26750A Registers
  6. 44CC Task Detailed Descriptions
    1. 4.1 Overview
    2. 4.2 CPU Control Tasks
      1. 4.2.1 'Gaid' - Return to normal operation
      2. 4.2.2 'GAID' - Cold reset request
    3. 4.3 PD Message Tasks
      1. 4.3.1  'SWSk' - PD PR_Swap to Sink
      2. 4.3.2  'SWSr' - PD PR_Swap to Source
      3. 4.3.3  'SWDF' - PD DR_Swap to DFP
      4. 4.3.4  'SWUF' - PD DR_Swap to UFP
      5. 4.3.5  'GSkC' - PD Get Sink Capabilities
      6. 4.3.6  'GSrC' - PD Get Source Capabilities
      7. 4.3.7  'ESkC' - PD EPR Get Sink Capabilities
      8. 4.3.8  'ESrC' - PD EPR Get Source Capabilities
      9. 4.3.9  'SSrC' - PD Send Source Capabilities
      10. 4.3.10 'GPPI' - PD Get Port Partner Information
      11. 4.3.11 'MBRd' - Message Buffer Read
    4. 4.4 Patch Bundle Update Tasks
      1. 4.4.1  'PBMs' - Start Patch Burst Mode Download Sequence
      2. 4.4.2  'PBMc' - Patch Burst Mode Download Complete
      3. 4.4.3  'PBMe' - End Patch Burst Mode Download Sequence
      4. 4.4.4  'GO2P' - Go to Patch Mode
      5. 4.4.5  'PTCs' - Start Patch Download Sequence
      6. 4.4.6  'PTCd' - Patch Download
      7. 4.4.7  'PTCc' - Patch Download Complete
      8. 4.4.8  'PTCq' - Patch Query
      9. 4.4.9  'PTCr' - Patch Reset
      10. 4.4.10 'FLrd' - Flash Memory Read
      11. 4.4.11 'FLad' - Flash Memory Write Start Address
      12. 4.4.12 'FLwd' - Flash Memory Write
      13. 4.4.13 'FLvy' - Flash Memory Verify
    5. 4.5 System Tasks
      1. 4.5.1 'ANeg' - Auto Negotiate Sink Update
      2. 4.5.2 'DBfg' - Clear Dead Battery Flag
      3. 4.5.3 'I2Cr' - I2C read transaction
      4. 4.5.4 'I2Cw' - I2C write transaction
      5. 4.5.5 'GPsh' - set GPIO high
      6. 4.5.6 'GPsl' - set GPIO low
  7. 5User Reference
    1. 5.1 PD Controller Application Customization
    2. 5.2 Loading a Patch Bundle
    3. 5.3 AUTO_NEGOTIATE_SINK Register
      1. 5.3.1 AUTO_NEGOTIATE_SINK Usage Example 1
      2. 5.3.2 AUTO_NEGOTIATE_SINK Usage Example 2
      3. 5.3.3 AUTO_NEGOTIATE_SINK Usage Example 3
      4. 5.3.4 AUTO_NEGOTIATE_SINK Usage Example 4
    4. 5.4 Liquid Detection Registers
    5. 5.5 GPIO Events
  8. 6Revision History

Liquid Detection Registers

Liquid detection control and status are contained in registers which can be read in the host interface. Settings for the liquid detection algorithm are changed when the algorithm is not running and remain static static when the algorithm is active. Liquid detection is run when the device is unattached and when the device is attached per user config. When the device is unattached and running liquid detection, the device runs liquid detection in active mode between sleep cycles and then returns to a lower power sleep mode if no liquid is detected.

The liquid detection external circuity is connected to LD1/LD2 for sensing the voltage differential on the ADC pins and a GPIO must be connected to the external circuit. The circuit is hooked up to pins from the USB Type-C Connector and can be used with used or unused pairs of signals, as well as a single signal.

The liquid detection configuration register (0x98) is used to configure and run the liquid detection algorithm. The liquid detection status register (0xb2) is used to monitor the status of the liquid detection algorithm and read any status updates that occur.

The algorithm drives the external circuit to VDD and GND to sense if the pins on the connector have been shorted to VBUS or GND. The sensing is done on two ADC input signals and an average is taken of the measurements to maintain accurate measurements. If a pin is shorted to a voltage that trips the OVP in T

The algorithm handles liquid detection and corrosion mitigation. In dead battery mode, corrosion mitigation is not allowed. To allow for corrosion mitigation, clear the dead battery flag. Corrosion mitigation sets the Type-C state machine into the Error Recoery state, where the CC terminations are set to Hi-Z. To remove this condition, the device must no longer sense liquid on the pins.

To configure the device for liquid detection, write to the following register fields:

Table 5-6 Liquid Detection Register 0x98 Field Parameters
Field Name Field Location Field Value
Wait Time in Seconds - Non-Liquid State 7:0 0xA
Wait Time in Seconds - Liquid State 15:8 0xA
Sample Time in 10ms - Non-Liquid State 19:16 0x1
Sample Time in 10ms - Liquid State 23:20 0x1
Liquid Detection Retries Wait Time in 100ms 27:24 0
Liquid Detection Retries 31:28 0
Number of Samples 39:32 3
Short to VDD Detection Threshold - Non-Liquid State 47:40 0x8f
Short to GND Detection Threshold - Non-Liquid State 55:48 0x24
Short to VDD Detection Threshold - Liquid State 63:56 0x8f
Short to GND Detection Threshold - Liquid State 71:64 0x24
Enable Liquid Detection 72 1
Enable Corrosion Mitigation 73 1
Monitor During Attach 74 1
Monitor During Unattach 75 1
Liquid Pins to Monitor 77:76 0