SNLU298 August   2021 DS320PR810

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
  3. 2Description
    1. 2.1 DS320PR810 5-Level I/O Control Inputs
    2. 2.2 DS320PR810 Modes of Operation
    3. 2.3 DS320PR810 SMBus or I2C Register Control Interface
    4. 2.4 DS320PR810 Equalization Control
    5. 2.5 DS320PR810-SMP-EVM Controls
    6. 2.6 Quick-Start Guide (Pin Mode)
    7. 2.7 Quick-Start Guide (SMBus Slave Mode)
  4. 3Schematics
  5. 4Board Layout
  6. 5Bill of Materials
  7. 6References

DS320PR810 SMBus or I2C Register Control Interface

The DS320PR810 internal registers can be accessed through standard SMBus protocol. The DS320PR810 features two banks of channels, Bank 0 (Channels 0–3) and Bank 1 (Channels 4–7), each featuring a separate register set and requiring a unique SMBus secondary address. The SMBus secondary address pairs (one for each channel bank) are determined at power up based on the configuration of the EQ0_0/ADDR1 and EQ1_0/ADDR0 pins. The pin state is read on power up, after the internal power-on reset signal is deasserted.

There are 16 unique SMBus secondary address pairs (one address for each channel bank) that can be assigned to the device by placing external resistor straps on the EQ0_0/ADDR1 and EQ1_0/ADDR0 pins as shown in Table 2-3. When multiple DS320PR810 devices are on the same SMBus interface bus, each channel bank of each device must be configured with a unique SMBus slave address pair. In this EVM,only Bank 0 channels are routed to SMP connectors, thus only Bank 0 registers need to be programmed.

Table 2-3 DS320PR810 SMBus Address Map
ADDR1 Pin LevelADDR0 Pin LevelBank 0: Channels 0-3:
7-Bit Address [HEX]
Bank 1 Channels 4-7:
7-Bit Address [HEX]
L0L00x180x19
L0L10x1A0x1B
L0L20x1C0x1D
L0L30x1E0x1F
L0L4ReservedReserved
L1L00x200x21
L1L10x220x23
L1L20x240x25
L1L30x260x27
L1L4ReservedReserved
L2L00x280x29
L2L10x2A0x2B
L2L20x2C0x2D
L2L30x2E0x2F
L2L4ReservedReserved
L3L00x300x31
L3L10x320x33
L3L20x340x35
L3L30x360x37
L3L4ReservedReserved