SNLA415 August   2022 DS160PT801

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2History
  5. 3Components of PCIe Communication
    1. 3.1 Root Complex
    2. 3.2 Repeater
    3. 3.3 Endpoints
  6. 4Signaling
    1. 4.1 PERST
    2. 4.2 WAKE and CLKREQ
    3. 4.3 REFCLK
  7. 5Link Training
    1. 5.1 Receiver Detect (Rx Detect)
    2. 5.2 Polling
    3. 5.3 Configuration
  8. 6Link Equalization
    1. 6.1 Phase 0 and 1
    2. 6.2 Phase 2 and 3
  9. 7Summary
  10. 8References

7 Summary

PCIe is an expansion bus that can communicate between CPU and various PCIe devices. It is a high-speed signal interface that can communicate up to 128 GT/s in PCIe 7.0. PCIe devices go through the link training process to establish connection among the root complex and the PCIe endpoints. This allows PCIe devices to send and receive data at PCIe Gen 1 data rate. If all connected PCIe devices are higher than Gen 3, PCIe devices will conduct link equalization processes to establish PCIe link at faster rates. Link equalization goes through initial tuning and fine tuning to allow bit error rate of less than 10-12 and send or receive data at the fastest rate it can stably support.