SNAU264 July   2021

 

  1. 1 Trademarks
  2. 2 General Description
    1. 2.1 Features
  3. 3 Quick Setup
    1. 3.1 Setup Procedure
  4. 4 Signal Path and Control Switches
  5. 5 Power Supplies
  6. 6 Clock Inputs
    1. 6.1 Configuring Board for CDCDB803
  7. 7 Clock Outputs
  8. 8 Using SMBus
    1. 8.1 CDCDB803 SMBus Address
  9. 9 Schematics
  10. 10Bill of Materials

2.1 Features

  • Easy-to-use evaluation board to fan out low-phase noise clocks

  • Simple, fast device configuration and setup

  • 8 LP-HCSL outputs with integrated 85-Ω output terminations

  • 8 hardware output enable (OE#) controls

  • DIP switch control of device configuration

  • Differential or single-ended input clock accepted

  • EVM supports all 8 differential LVDS outputs. Both output banks are available for testing by default