SLVUD30A December   2024  – December 2025 TPS65214

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521401 Power Sequence and Example Block Diagram
  6. 3NVM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Low Power Mode
  7. 4Revision History

3.7 Over-Current Deglitch

This section describes the default settings for the over current deglitch. When any of these registers are set (value = 1b), it enables the long-deglitch option for the corresponding rail.

Table 3-13 Over Current Deglitch
Register AddressField NameValueDescription
0x23EN_LONG_DEGL_FOR_OC_BUCK10x0Deglitch duration for OverCurrent on BUCK1 is ~20us
0x23EN_LONG_DEGL_FOR_OC_BUCK20x0Deglitch duration for OverCurrent on BUCK2 is ~20us
0x23EN_LONG_DEGL_FOR_OC_BUCK30x0Deglitch duration for OverCurrent on BUCK3 is ~20us