SLVUD30A December   2024  – December 2025 TPS65214

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521401 Power Sequence and Example Block Diagram
  6. 3NVM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Low Power Mode
  7. 4Revision History

3.4.2 Power-Down Sequence

Table 3-8 Power-Down Sequence - Slot Assignment
Register AddressField NameValueDescription
BUCK10x11BUCK1_SEQUENCE_OFF_SLOT0x2slot 2
BUCK20x10BUCK2_SEQUENCE_OFF_SLOT0x2slot 2
BUCK30x0FBUCK3_SEQUENCE_OFF_SLOT0x0slot 0
LDO10x0CLDO1_SEQUENCE_OFF_SLOT0x2slot 2
LDO20x0D LDO2_SEQUENCE_OFF_SLOT0x3slot 3
GPO10x15GPO1_SEQUENCE_OFF_SLOT0x0slot 0
GPIO0x13GPIO_SEQUENCE_OFF_SLOT0x3slot 3
nRSTOUT0x12 nRST_SEQUENCE_OFF_SLOT0x0slot 0
Table 3-9 Power-Down Sequence - Slot Duration
Register AddressField NameValueDescription
SLOT00x16POWER_DOWN_SLOT_0_DURATION0x310ms
SLOT10x16POWER_DOWN_SLOT_1_DURATION0x00ms
SLOT20x16POWER_DOWN_SLOT_2_DURATION0x310ms
SLOT30x16POWER_DOWN_SLOT_3_DURATION0x00ms
SLOT40x17POWER_DOWN_SLOT_4_DURATION0x00ms
SLOT50x17POWER_DOWN_SLOT_5_DURATION0x00ms
SLOT60x17POWER_DOWN_SLOT_6_DURATION0x00ms
SLOT70x17POWER_DOWN_SLOT_7_DURATION0x00ms