SLVUD30A December   2024  – December 2025 TPS65214

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521401 Power Sequence and Example Block Diagram
  6. 3NVM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Low Power Mode
  7. 4Revision History

3.1 Device ID

This section lists all the register settings that identify the supported temperature and the NVM ID with the corresponding revision that represents a list of default register settings.

Table 3-1 Device ID
Register AddressField NameValueDescription
0x00 NVM_REVISION

(Bits: 7-5)

 0x2 Identification code for the NVM revision
0x00 TI_DEVICE_ID

(Bits: 4-0)

 0x04 Device specific ID code.
0x01TI_NVM_ID

(Bits: 7-0)

0x01Identification code for the NVM ID
0x26I2C_ADDRESS

(Bits: 6-0)

0x30I2C address