SLVUD30A December   2024  – December 2025 TPS65214

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521401 Power Sequence and Example Block Diagram
  6. 3NVM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Low Power Mode
  7. 4Revision History

3.8 Mask Settings

This section describes the settings that are masked by default and the effect they have on the device state as well as the nINT pin.

Table 3-14 Mask Settings
Register AddressField NameValueDescription
Mask effects on device state and nINT pin0x25MASK_EFFECT0x03no state change, nINT reaction, bit set for Faults
UV Mask0x24BUCK1_UV_MASK0x0un-masked (Faults reported)
0x24BUCK2_UV_MASK0x0un-masked (Faults reported)
0x24BUCK3_UV_MASK0x0un-masked (Faults reported)
0x24LDO1_UV_MASK0x0un-masked (Faults reported)
0x24LDO2_UV_MASK0x0un-masked (Faults reported)
Power-up retries/attempts 0x20 MASK_RETRY_COUNT_ON_FIRST_PU 0x0 RETRY_COUNT is not masked on first power-up.
0x24 MASK_RETRY_COUNT 0x0 Device retries up to 2 times
Die Temperature0x25SENSOR_0_WARM_MASK0x0un-masked (Faults reported)
0x25SENSOR_1_WARM_MASK0x0un-masked (Faults reported)
0x25SENSOR_2_WARM_MASK0x0un-masked (Faults reported)
Masking bit to control whether nINT pin is sensitive to PushButton (PB)0x25MASK_INT_FOR_PB0x1masked (nINT pin not sensitive to any PB events)
Masking bit to control whether nINT pin is sensitive to RV (Residual Voltage) 0x25MASK_INT_FOR_RV0x0un-masked (nINT pin pulled low for any RV events during transition to ACTIVE state or during enabling of rails)