SLVUCL7 December   2022 TPS631010

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification
    3. 1.3 Modifications
      1. 1.3.1 IC U1 Operation
      2. 1.3.2 Device Enable Evaluation
  4. 2Setup
    1. 2.1 Input/Output Connector and Header Descriptions
    2. 2.2 Setup
  5. 3Board Layout
    1. 3.1 Layout
  6. 4Schematic and Bill of Materials
    1. 4.1 Schematic
  7. 5Bill of Materials

3.1 Layout

Figure 3-1 and Figure 3-2 show the board layout for the TPS631010EVM PCB.

Figure 3-1 Top Layer Routing
Figure 3-2 Bottom Layer Routing