SLVUAH4A August   2015  – October 2021 TPS54334

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification Summary
    3. 1.3 Modifications
      1. 1.3.1 Output Voltage Set Point
      2. 1.3.2 Adjustable UVLO
  3. 2Test Setup and Results
    1. 2.1  Input/Output Connections
    2. 2.2  Efficiency
    3. 2.3  Output Voltage Load Regulation
    4. 2.4  Output Voltage Line Regulation
    5. 2.5  Load Transients
    6. 2.6  Loop Characteristics
    7. 2.7  Output Voltage Ripple
    8. 2.8  Input Voltage Ripple
    9. 2.9  Powering Up
    10. 2.10 Powering Down
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
  6. 5Revision History

2.1 Input/Output Connections

The TPS54334EVM-722 is provided with input/output connectors and test points as shown in Table 2-1. A power supply capable of supplying 2 A must be connected to J1 through a pair of 20-AWG wires. The load must be connected to J4 through a pair of 20-AWG wires. The maximum load current capability must be at least 4 A to use the full capability of this EVM. Wire lengths must be minimized to reduce losses in the wires. Test-point TP1 provides a place to monitor the VIN input voltages with TP2 providing a convenient ground reference. TP6 is used to monitor the output voltage with TP7 as the ground reference.

Table 2-1 EVM Connectors and Test Points
Reference DesignatorFunction
J1VIN (see Table 1-1 for VIN range)
J2VOUT, 3.3 V at 3 A maximum
JP12-pin header for enable. Connect EN to ground to disable, open to enable.
JP22-pin header for VDD. Connect VOUT to VDD as the power supply.
TP1VIN test point at VIN connector
TP2GND test point at VIN
TP3PGOOD test point
TP4PH test point
TP5Test point between voltage divider network and output. Used for loop response measurements.
TP6Output voltage test point at OUT connector
TP7GND test point at VOUT connector
TP8VDD test point at the VDD connector
TP9GND test point at the VDD connector
TP10EN test point