SLLA498 October 2020
Table 5-1 compares and summarizes the previously-discussed inverter topologies.
2-Level H-Bridge | HERIC | 3-Level TNPC | 3-Level NPC | 3-Level ANPC | |
|---|---|---|---|---|---|
THD of output | High | Low | Low | Low | Low |
Peak stress on devices | High | Low /(High Blocking) | Low /(High Blocking) | Low | Low |
Power density | Low | Medium | High | High | Highest |
Bidirectional | Yes | Yes | Yes | Yes | Yes |
Conduction loss | Low | Medium | Medium | High | Medium |
Switching loss | High | Medium | Medium | Low | Low |
Efficiency | Low | High | High | High (at high frequency) | High (at high frequency) |
Switching Frequency | Low | Medium | Medium | High | High |
Cost | Low | Medium | Medium | High | Highest |
Control | Easy | Medium | Medium | Medium | Complex |
Inductor size | Large | Medium | Medium | Small | Small |
EMI | High | Medium (high dv/dt) | Medium (high dv/dt) | Low | Low |
Thermal management | Easy | Easy | Easy | Difficult | Easy |