SLAU647O July   2015  – April 2020

 

  1.   MSP Debuggers
    1.     Trademarks
    2. 1 Introduction
      1. 1.1 Related Documentation From Texas Instruments
      2. 1.2 Terms and Abbreviations
      3. 1.3 If You Need Assistance
    3. 2 MSP Debug Probe Overview
      1. 2.1 Known Limitations
    4. 3 Hardware Identification
      1. 3.1 How to Determine If Your Hardware is Based on eZ-FET or eZ-FET Lite
      2. 3.2 How to Determine If Your Hardware is Based on eZ430
      3. 3.3 Signal Connections for In-System Programming and Debugging
      4. 3.4 Using the Power Supply Feature of the eZ-FET and eZ-FET Lite
      5. 3.5 Using the Power Supply Feature of the MSP-FET430UIF and MSP-FET
    5. 4 Hardware Installation
      1. 4.1 MSP-FET430PIF
      2. 4.2 MSP-FET430UIF, MSP-FET, eZ-FET, and eZ-FET Lite
      3. 4.3 eZ430-Based Experimenter Boards and LaunchPad Kits
      4. 4.4 Hardware Installation Using the MSP Flasher
      5. 4.5 Hardware Installation Using CCS Cloud
    6. 5 Debug Probes Hardware and Software
      1. 5.1  MSPDebugStack
      2. 5.2  Ultra-Low-Power (ULP) Debug Support
      3. 5.3  EnergyTrace™ Technology
      4. 5.4  Unlimited Software Breakpoints in Flash, FRAM, and RAM
      5. 5.5  JTAG Access Protection (Fuse Blow)
      6. 5.6  MSP-FET Stand-Alone Debug Probe
        1. 5.6.1 General Features
        2. 5.6.2 Backchannel UART
          1. 5.6.2.1 UART Backchannel Activation Commands
        3. 5.6.3 Target BSL Connection and BSL-Scripter Support
        4. 5.6.4 LED Signals
        5. 5.6.5 Hardware
          1. 5.6.5.1 JTAG Target Connector
          2. 5.6.5.2 MSP-FET Pin States After Power Up
          3. 5.6.5.3 MSP-FET HID Cold Boot
          4. 5.6.5.4 Schematics
            1. 5.6.5.4.1 MSP-FET Rev 2.5 Schematics
            2. 5.6.5.4.2 MSP-FET Rev 1.2 Schematics
        6. 5.6.6 Specifications
          1. 5.6.6.1 Hardware
          2. 5.6.6.2 MSP430 MCUs
          3. 5.6.6.3 SimpleLink MSP432 MCUs
      7. 5.7  MSP-FET430UIF Stand-Alone Debugger
        1. 5.7.1 General Features
        2. 5.7.2 LED Signals
        3. 5.7.3 Hardware
          1. 5.7.3.1 JTAG Target Connector
          2. 5.7.3.2 Pin States After Power Up
          3. 5.7.3.3 Schematics
      8. 5.8  eZ-FET and eZ-FET Lite Onboard Emulation
        1. 5.8.1 General Features
        2. 5.8.2 Backchannel UART
          1. 5.8.2.1 eZ-FET and eZ-FET Lite UART Backchannel Activation Commands
        3. 5.8.3 LED Signals
        4. 5.8.4 Hardware
          1. 5.8.4.1 JTAG Target Connector
          2. 5.8.4.2 Connecting MSP-FET to LaunchPad Development Kit
          3. 5.8.4.3 Pin States After Power Up
          4. 5.8.4.4 Schematics
            1. 5.8.4.4.1 eZ-FET Rev 1.2 Schematics
            2. 5.8.4.4.2 eZ-FET Lite Schematics
            3. 5.8.4.4.3 eZ-FET Rev 1.4 Schematic
            4. 5.8.4.4.4 eZ-FET Rev 2.0 ET Schematics
      9. 5.9  eZ430 Onboard Emulation
        1. 5.9.1 General Features
        2. 5.9.2 Backchannel UART
        3. 5.9.3 Hardware
          1. 5.9.3.1 JTAG Target Connector
          2. 5.9.3.2 Pin States After Power Up
          3. 5.9.3.3 Schematics
      10. 5.10 MSP-FET430PIF
        1. 5.10.1 General Features
        2. 5.10.2 Schematics
  2.   Revision History

5.7.3.2 Pin States After Power Up

Table 13 describes the electrical state of every JTAG pin after debug probe power up.

Table 13. MSP-FET430UIF Pin States

Pin Name After Power-Up When JTAG Protocol is Active When Spy-Bi-Wire Protocol is Active
1 TDO/TDI Hi-Z, pulled up to 3.3 V In, TDO In and Out, SBWTDIO
2 VCC_TOOL 3.3 V Target VCC Target VCC
3 TDI/VPP Hi-Z, pulled up to 3.3 V Out, TDI Hi-Z, pulled up to VCC
4 VCC_TARGET In, external VCC sense In, external VCC sense In, external VCC sense
5 TMS Hi-Z, pulled up to 3.3 V Out, TMS Hi-Z, pulled up to VCC
6 N/C N/C N/C N/C
7 TCK Hi-Z, pulled up to 3.3 V Out, TCK Out, SBWTCK
8 TEST/VPP Out, Ground Out, TEST Hi-Z, pulled up to VCC
9 GND Ground Ground Ground
10 N/C N/C N/C N/C
11 RST Out, VCC Out, RST Ground
12 N/C N/C N/C N/C
13 N/C N/C N/C N/C
14 N/C N/C N/C N/C