SLAAES1 April   2026 TAA5212 , TAC5112 , TAC5112-Q1 , TAC5212

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1 What is an Incremental ADC (IADC)?
    2. 2.2 IADC Operation
      1. 2.2.1 RESET
      2. 2.2.2 SKIP
      3. 2.2.3 CONVERT
    3. 2.3 IADC Modes of Operation
    4. 2.4 Test Examples Using TAC5212EVM-K
      1. 2.4.1 One-Shot, Single Channel Conversion
      2. 2.4.2 One-Shot, Multichannel Conversion
      3. 2.4.3 One-Shot Conversion Using GPIO2
      4. 2.4.4 Sequential, Single Channel Conversion
      5. 2.4.5 Sequential, Multichannel Conversion
      6. 2.4.6 Impact of OSR on the IADC Output
  6. 3Summary
  7. 4References

2.3 IADC Modes of Operation

The IADC can operate in four different modes of operation, each selectable through the IADC_MODE field (B0_P0_R81[6:5]), shown in Table 2-2.

  1. One-shot Single Channel Mode: In this mode of operation, the device does a single conversion on a single channel per ADC. Hence, for a stereo ADC, two channels are converted together. The conversion is initiated as described in IADC Operation, and the status of conversion can be monitored by reading the IADC_ONESHOT_CONV_ DONE_STS bit. The result can be read back on the registers described in CONVERT. The channel which is being converted is selected through the ADC_CHx_INSRC in SE_MUX mode (INxP/INxM).
  2. One-shot Multichannel Mode: In this mode of operation, the device does a single conversion on all the input channels. For a stereo ADC, four inputs (IN1P, IN1M, IN2P, IN2M) are digitized. The conversion is initiated as described in IADC Operation, and the status of conversion can be monitored by reading the IADC_ONESHOT_CONV_ DONE_STS bit. The result can be read back on the registers described in CONVERT.
  3. Sequential Single Channel Conversion: In this mode of operation the device continuously converts the input voltage from the selected channels. Setting the IADC_STOP_SEQ_CONV bit (B0_P0_R81[3]) stops this conversion. Clearing this bit again resumes the conversion. In sequential mode, the IADC automatically goes through the RESET-SKIP-CONVERT-RESET-SKIP… cycles.
  4. Sequential Multichannel Conversion: In this mode of operation the device continuously converts the input voltage from all the input channels. Setting the IADC_STOP_SEQ_CONV bit (B0_P0_R81[3]) stops this conversion. Clearing this bit again resumes the conversion.

    Setting the HOLD_IADC_DATA (B0_P1_R85[2]) holds the previously converted data in the registers. After reading back these values, this bit can be cleared to enable register update with freshly converted values. Until this bit is cleared, the register does not get updated with any fresh conversion data.