SLAAES1 April   2026 TAA5212 , TAC5112 , TAC5112-Q1 , TAC5212

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1 What is an Incremental ADC (IADC)?
    2. 2.2 IADC Operation
      1. 2.2.1 RESET
      2. 2.2.2 SKIP
      3. 2.2.3 CONVERT
    3. 2.3 IADC Modes of Operation
    4. 2.4 Test Examples Using TAC5212EVM-K
      1. 2.4.1 One-Shot, Single Channel Conversion
      2. 2.4.2 One-Shot, Multichannel Conversion
      3. 2.4.3 One-Shot Conversion Using GPIO2
      4. 2.4.4 Sequential, Single Channel Conversion
      5. 2.4.5 Sequential, Multichannel Conversion
      6. 2.4.6 Impact of OSR on the IADC Output
  6. 3Summary
  7. 4References

2.2 IADC Operation

Table 2-1, Table 2-2 and Table 2-3 list out the different registers for configuring IADC, describing the individual bit fields and their functionality.

The IADC mode is enabled by setting the IADC_EN bit in B0_P0_R81 register. The user initiates start of conversion in two ways:

  1. For one-shot conversion, setting the IADC_CONVST_ONESHOT bit (B0_P0_R81[4] starts the conversion.
  2. The CONVST (CONversion STart) signal can also be provided through a GPIO pin. To use GPIO1 as a CONVST signal for the IADC:
    1. Configure the GPIO1 pin as a general-purpose input (GPI) or any other input function be setting the GPIO1_CFG[3:0] field to 1(B0_P0_R10[7:4]).
    2. Enable IADC using GPIO1 by setting the IADC_CONVST_GPIO[1:0] field to 1 (B0_P0_R21[5:4]).

The IADC_ONESHOT_CONV_DONE_STS bit (B0_P0_R81[2]) gives out the status of completion of the IADC conversion.

The IADC operates in three distinct phases, which are described in further sections:

  1. The RESET phase
  2. The SKIP phase
  3. The CONVERT phase
Table 2-1 IADC_CFG Register (Book 0, Page 0, Register 76)
Bit Field Type Reset Description
7-5 IADC_NSKIP_SEL[1:0] R/W 001b ADC NSKIP configuration.
0d = 384 mod clks
1d = 576 mod clks
2d = 896 mod clks
3d = 1024 mod clks
4d = 2048 mod clks
5d = 4096 mod clks
6d-7d = Reserved
4-3 IADC_NRESET_SEL[1:0] R/W 01b IADC NRESET configuration.
0d = 50 mod clks
1d = 75 mod clks
2d = 100 mod clks
3d = 150 mod clks
2-1 IADC_OSR_SEL[1:0] R/W 11b IADC OSR select configuration.
0d = 32
1d = 64
2d = 96
3d = 128
0 RESERVED R 0b Reserved bits; Write only reset value
Table 2-2 IADC_CH_CFG Register (Book 0, Page 0, Register 81)
Bit Field Type Reset Description
7IADC_ENR/W0bIADC enable configuration.
0d = IADC disabled
1d = IADC enabled
6-5IADC_MODE[1:0]R/W00bIADC mode configuration. (for single channel mode channel select is controlled by ADC_INSRC_SE_MUX config)
0d = One-shot single channel
1d = One-shot multichannel
2d = Sequential single channel
3d = Sequential multichannel
4IADC_CONVST_ONESHOTR/W0bIADC conversion start one short configuration.
0d = No conversion
1d = Start one shot conversion
3IADC_STOP_SEQ_CONVR/W0bIADC stop sequential conversion configuration.
0d = Sequential conversion running
1d = Stop sequential conversion
2IADC_ONESHOT_CONV_ DONE_STSR/W0bIADC one shot conversion done configuration.
0d = Conversion not done
1d = One shot conversion done
1-0RESERVEDR0bReserved bits; Write only reset value
Table 2-3 INTF_CFG6 Register Field for IADC (Book 0, Page 0, Register 21)
Bit Field Type Reset Description
5-4IADC_CONVST_GPIO[1:0]R/W00bIADC conversion start using GPIO select configuration.
0d = Enable IADC using GPIO is disabled
1d = Enable IADC using GPIO1
2d = Enable IADC using GPIO2
3d = Enable IADC using GPI1

A Single IADC Conversion Cycle represents the sequence of operations when an IADC conversion is initiated. Each phase operates for a certain number of modulator clock cycles. Hence the total conversion time for the IADC is:

Equation 1. TCONV_IADC=NRESET+NSKIP+NCONVModulatorClockFrequency
A Single IADC Conversion CycleFigure 2-1 A Single IADC Conversion Cycle