SLAAES1 April   2026 TAA5212 , TAC5112 , TAC5112-Q1 , TAC5212

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1 What is an Incremental ADC (IADC)?
    2. 2.2 IADC Operation
      1. 2.2.1 RESET
      2. 2.2.2 SKIP
      3. 2.2.3 CONVERT
    3. 2.3 IADC Modes of Operation
    4. 2.4 Test Examples Using TAC5212EVM-K
      1. 2.4.1 One-Shot, Single Channel Conversion
      2. 2.4.2 One-Shot, Multichannel Conversion
      3. 2.4.3 One-Shot Conversion Using GPIO2
      4. 2.4.4 Sequential, Single Channel Conversion
      5. 2.4.5 Sequential, Multichannel Conversion
      6. 2.4.6 Impact of OSR on the IADC Output
  6. 3Summary
  7. 4References

2.2.3 CONVERT

After skipping the first NSKIP samples, the IADC converts the input a further NOSR modulator clock cycles, where OSR stands for Over-Sampling Ratio. These individual samples are stored in the internal memory and are then averaged to obtain the result. The NOSR can be provided as an input in the register field B0_P0_R76[2:1], shown in Table 2-1.

At the end of the "CONVERT" phase, the digital output code is available for readback. Setting the IADC_DATA_IN_DIAG_REGS bit (B0_P1_R85[3]) enables storing of the 24-bit digital code into the following registers:

  1. B0_P1_R98-100 contains the 24-bit digital code for IADC CH1.
  2. B0_P1_R101-103 contains the 24-bit digital code for IADC CH2.
  3. B0_P1_R104-106 contains the 24-bit digital code for IADC CH3.
  4. B0_P1_R107-109 contains the 24-bit digital code for IADC CH4.

The 24-bit signed integer x can be used to calculate the input voltage by following the below equation:

Equation 2. v = x * 0.925 2 22 * 2 * 5.6569 + 1.375 V

The input to the IADC can range from 0V to 5.6V for each pin.