SLAAES1 April   2026 TAA5212 , TAC5112 , TAC5112-Q1 , TAC5212

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1 What is an Incremental ADC (IADC)?
    2. 2.2 IADC Operation
      1. 2.2.1 RESET
      2. 2.2.2 SKIP
      3. 2.2.3 CONVERT
    3. 2.3 IADC Modes of Operation
    4. 2.4 Test Examples Using TAC5212EVM-K
      1. 2.4.1 One-Shot, Single Channel Conversion
      2. 2.4.2 One-Shot, Multichannel Conversion
      3. 2.4.3 One-Shot Conversion Using GPIO2
      4. 2.4.4 Sequential, Single Channel Conversion
      5. 2.4.5 Sequential, Multichannel Conversion
      6. 2.4.6 Impact of OSR on the IADC Output
  6. 3Summary
  7. 4References

1 Introduction

In audio applications, a dynamic analog signal is typically digitized continuously by a delta-sigma analog-to-digital converter (ADC) followed by a decimation filter. This makes sure that the moving signal is captured at a sampling rate that covers the signal bandwidth.

However, in non-audio applications such as sensing, delta-sigma ADCs are mainly used to provide low-noise measurements for DC or slow-moving signals.

This application note describes the different ways to configure the ADC in the TAx5x1x/TAx5x1x-Q1 devices as Incremental ADCs (IADCs) for such applications.