SLAA517F May   2012  – August 2021 MSP430F6720A , MSP430F6720A , MSP430F6721A , MSP430F6721A , MSP430F6723A , MSP430F6723A , MSP430F6724A , MSP430F6724A , MSP430F6725A , MSP430F6725A , MSP430F6726A , MSP430F6726A , MSP430F6730A , MSP430F6730A , MSP430F6731A , MSP430F6731A , MSP430F6733A , MSP430F6733A , MSP430F6734A , MSP430F6734A , MSP430F6735A , MSP430F6735A , MSP430F6736 , MSP430F6736 , MSP430F6736A , MSP430F6736A

 

  1.   Trademarks
  2. 1Introduction
  3. 2System Diagrams
  4. 3Hardware Implementation
    1. 3.1 Power Supply
      1. 3.1.1 Resistor Capacitor (RC) Power Supply
    2. 3.2 Analog Inputs
      1. 3.2.1 Voltage Inputs
      2. 3.2.2 Current Inputs
  5. 4Software Implementation
    1. 4.1 Peripherals Setup
      1. 4.1.1 SD24 Setup
    2. 4.2 Foreground Process
      1. 4.2.1 Formulas
        1. 4.2.1.1 Voltage and Current
        2. 4.2.1.2 Power and Energy
    3. 4.3 Background Process
      1. 4.3.1 Voltage and Current Signals
      2. 4.3.2 Phase Compensation
      3. 4.3.3 Frequency Measurement and Cycle Tracking
      4. 4.3.4 LED Pulse Generation
  6. 5Energy Meter Demo
    1. 5.1 EVM Overview
      1. 5.1.1 Connections to the Test Setup for AC Voltages
      2. 5.1.2 Power Supply Options and Jumper Settings
    2. 5.2 Loading the Example Code
      1. 5.2.1 Opening the Project
  7. 6Results and Calibration
    1. 6.1 Viewing Results
    2. 6.2 Calibrating the Meter
      1. 6.2.1 Gain Correction
      2. 6.2.2 Phase Correction
      3. 6.2.3 Metrology Results
  8. 7References
  9. 8Schematics
  10. 9Revision History

4.3.2 Phase Compensation

The Current Transformer (CT) when used as a sensor and the input circuit’s passive components together introduces an additional phase shift between the current and voltage signals that needs compensation. The ΣΔ converter has built in hardware delay that can be applied to individual samples when grouped. This can be used to provide the phase compensation required. This value is obtained during calibration and loaded on to the respective PRELOAD register for each converter. Figure 4-3 shows the application of PRELOAD (SD24PREx).

GUID-725B950C-D38D-43CB-A391-AF925695EE15-low.gif Figure 4-3 Phase Compensation Using PRELOAD Register

The fractional delay resolution is a function of input line frequency (fIN), OSR and the sampling frequency (fS).

Equation 6. Delay resolution Deg = 360°×f IN OSR×f S = 360°×f IN f M

In the current application for input frequency of 60 Hz, OSR of 256 and sampling frequency of 4096, the resolution for every bit in the preload register is about 0.02° with a maximum of 5.25° (maximum of 255 steps). Since the sampling of the 3 channels are group triggered, an often method used is to apply 128 steps of delay to all channels and then increasing or decreasing from this base value. This allows ± delay timing to compensate for phase lead or lag. This puts the practical limit in the current design to ± 2.62°. When using CTs that provide a larger phase shift than this maximum, an entire sample delay along with fractional delay must be provided. This phase compensation can also be modified on the fly to accommodate temperature drifts in CTs.