SLAA249B April   2005  – September 2018 MSP430F169 , MSP430F169 , MSP430F5252 , MSP430F5252 , MSP430F5253 , MSP430F5253 , MSP430F5254 , MSP430F5254 , MSP430F5255 , MSP430F5255 , MSP430F5256 , MSP430F5256 , MSP430F5257 , MSP430F5257 , MSP430F5258 , MSP430F5258 , MSP430F5259 , MSP430F5259

 

  1.   Implementing SMBus Using MSP430™ Hardware I2C
    1.     Trademarks
    2. 1 Introduction
    3. 2 SMBus Protocols
    4. 3 Software
    5. 4 Example Code
      1. 4.1 Example 1
        1.       fet140_SMB_mstr.c(.s43)
        2.       fet140_SMB_slav.c(.s43)
      2. 4.2 Example 2
        1.       fet140_SMB_mstr_slvrst.c(.s43)
        2.       fet140_SMB_slav_slvrst.c(.s43)
      3. 4.3 Example 3
        1.       fet140_SMB_mstr_PEC.c
        2.       fet140_SMB_slave_PEC.c
      4. 4.4 Example 4
        1.       fet140_SMB_tmp175.c
    6. 5 SMBus Using the USCI I2C Peripheral
      1. 5.1 Example 1a: Timeout Implementation for Master/Slave on a MSP430F2xx Device
        1.       msp430x26x_SMB_MST_timeout.c
        2.       msp430x26x_SMB_SLV_timeout.c
      2. 5.2 Example 1b: Timeout Implementation for Master/Slave on a MSP430F5xx Device
        1.       msp430x5xx_SMB_MST_timeout.c
        2.       msp430x5xx_SMB_SLV_timeout.c
      3. 5.3 Example 2: Implementation of CRC-8 PEC
        1.       msp430x26x_SMB_mstr_PEC.c
        2.       msp430x26x_SMB_slave_PEC.c
      4. 5.4 Example 3: Implementation With SMBUS Slave TMP175
        1.       msp430x26x_SMB_tmp175.c
    7. 6 Conclusion
    8. 7 References
  2.   Revision History

2 SMBus Protocols

The different communication protocols can be found in the System Management Bus specification. [2] The communication always begins with a valid start condition from the master followed by a 7-bit slave address and the read/write bit that defines the master as a receiver /transmitter respectively, except in the quick command protocol. In quick command protocol, the read/write bit is used to turn a device on/off or enable/disable a low-power mode. The read/write bit is followed by an Acknowledge from the slave. This is followed by 8-bit transfers that may be data, command, or Packet Error Check (PEC). An acknowledge is sent by the receiver after each byte is received. To end the transfer, a valid stop condition is initiated by the master.

The SMBus standard introduced the Packet Error Checking (PEC) mechanism to improve communication reliability. The PEC is a CRC-8 error check byte, calculated on all message bytes except the ACK, NACK, START, and STOP bits. The PEC is added to the message by the transmitter. The PEC in this application report is calculated using a cyclic redundancy check (CRC-8) polynomial, C(x) = x8 + x2 + x1+ 1 and is calculated bit by bit in the order of bits received. See the SMBus specification for details on the PEC.

Another optional signal defined in the SMBus standard is the SMBALERT signal. This pin is also pulled up to VCC through a resistor. A slave device can signal the master through SMBALERT to request communication with the master. The master acknowledges such a slave device by sending the SMBus alert response address (0001 1001b) on the bus. The slave device acknowledges this Alert command by returning its 7-bit slave address on the bus and the ALERT signal becomes inactive. The eighth bit can be a 0 or 1. If multiple devices pull the SMBALERT signal low, the lowest address device wins arbitration, and its signal becomes inactive after the corresponding slave address byte is put on the bus.

The SMBus operating frequency range is 10 kHz to 100 kHz. Because a minimum speed needs to be maintained in this communication, a slave can hold SCL low for only a specified amount of time before the master times out and issues a stop condition. A slave can hold the clock low for 25 ms before timeout occurs. After this time, the slave must be able to receive a new start condition within 35 ms. Additional timing information can be found on the SMBus specification site (http://www.smbus.org). [2]