SLAA249B April   2005  – September 2018 MSP430F169 , MSP430F169 , MSP430F5252 , MSP430F5252 , MSP430F5253 , MSP430F5253 , MSP430F5254 , MSP430F5254 , MSP430F5255 , MSP430F5255 , MSP430F5256 , MSP430F5256 , MSP430F5257 , MSP430F5257 , MSP430F5258 , MSP430F5258 , MSP430F5259 , MSP430F5259

 

  1.   Implementing SMBus Using MSP430™ Hardware I2C
    1.     Trademarks
    2. 1 Introduction
    3. 2 SMBus Protocols
    4. 3 Software
    5. 4 Example Code
      1. 4.1 Example 1
        1.       fet140_SMB_mstr.c(.s43)
        2.       fet140_SMB_slav.c(.s43)
      2. 4.2 Example 2
        1.       fet140_SMB_mstr_slvrst.c(.s43)
        2.       fet140_SMB_slav_slvrst.c(.s43)
      3. 4.3 Example 3
        1.       fet140_SMB_mstr_PEC.c
        2.       fet140_SMB_slave_PEC.c
      4. 4.4 Example 4
        1.       fet140_SMB_tmp175.c
    6. 5 SMBus Using the USCI I2C Peripheral
      1. 5.1 Example 1a: Timeout Implementation for Master/Slave on a MSP430F2xx Device
        1.       msp430x26x_SMB_MST_timeout.c
        2.       msp430x26x_SMB_SLV_timeout.c
      2. 5.2 Example 1b: Timeout Implementation for Master/Slave on a MSP430F5xx Device
        1.       msp430x5xx_SMB_MST_timeout.c
        2.       msp430x5xx_SMB_SLV_timeout.c
      3. 5.3 Example 2: Implementation of CRC-8 PEC
        1.       msp430x26x_SMB_mstr_PEC.c
        2.       msp430x26x_SMB_slave_PEC.c
      4. 5.4 Example 3: Implementation With SMBUS Slave TMP175
        1.       msp430x26x_SMB_tmp175.c
    7. 6 Conclusion
    8. 7 References
  2.   Revision History

msp430x26x_SMB_SLV_timeout.c

This is the slave code source for the master code in msp430x26x_SMB_MST_timeout.c. The slave receives one byte and transmits two bytes to the master. After the first byte is transmitted, the transmit interrupt enable (UCBxTXIE) is disabled to prevent the slave from sending the second byte and causing the clock line (SCL) to be held low during that period exercising the timeout features of the SMBus protocol. This creates a timeout condition. The master and slave on detecting the timeout proceed to reset the USCI logic allowing the I2C bus to be released. The functionality following a timeout can be varied as required by the user. On reset of the USCI module, the slave stays in LPM4 waiting for an instruction from the master, making use of the automatic clock activation feature on this device. In order to transmit and receive bytes without simulating a timeout, the user can comment out the following line in the TX ISR in the example:

// IE2 &= ~UCB0TXIE; // Read the comment below

This is also documented in the code.