SLAA249B April 2005 – September 2018 MSP430F169 , MSP430F169 , MSP430F5252 , MSP430F5252 , MSP430F5253 , MSP430F5253 , MSP430F5254 , MSP430F5254 , MSP430F5255 , MSP430F5255 , MSP430F5256 , MSP430F5256 , MSP430F5257 , MSP430F5257 , MSP430F5258 , MSP430F5258 , MSP430F5259 , MSP430F5259
This is the slave code source for the master code in msp430x26x_SMB_MST_timeout.c. The slave receives one byte and transmits two bytes to the master. After the first byte is transmitted, the transmit interrupt enable (UCBxTXIE) is disabled to prevent the slave from sending the second byte and causing the clock line (SCL) to be held low during that period exercising the timeout features of the SMBus protocol. This creates a timeout condition. The master and slave on detecting the timeout proceed to reset the USCI logic allowing the I2C bus to be released. The functionality following a timeout can be varied as required by the user. On reset of the USCI module, the slave stays in LPM4 waiting for an instruction from the master, making use of the automatic clock activation feature on this device. In order to transmit and receive bytes without simulating a timeout, the user can comment out the following line in the TX ISR in the example:
// IE2 &= ~UCB0TXIE; // Read the comment below
This is also documented in the code.