SLAA249B April 2005 – September 2018 MSP430F169 , MSP430F169 , MSP430F5252 , MSP430F5252 , MSP430F5253 , MSP430F5253 , MSP430F5254 , MSP430F5254 , MSP430F5255 , MSP430F5255 , MSP430F5256 , MSP430F5256 , MSP430F5257 , MSP430F5257 , MSP430F5258 , MSP430F5258 , MSP430F5259 , MSP430F5259
The master is the receiver and detects a timeout due to the slave holding the clock line low for a period greater than "timeout". TimerA0 is used to detect this timeout period, and the master issues a stop condition at the conclusion of the byte transfer currently in progress.
The hardware I2C has the built-in I2CBB (Bus Busy) bit that is set after a start condition. I2CBB and I2CSCLLOW may be used to determine how long SCL has been held low after a start condition. The corresponding slave code source file is fet140_SMB_slav.c.