SFFS983A August   2025  â€“ October 2026 MSPM0G1518 , MSPM0G1519 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0G3529-Q1

 

  1.   1
  2. 1Introduction
    1.     Trademarks
  3. 2MSPM0Gx51x and MSPM0Gx52x Hardware Component Functional Safety Capability
  4. 3Development Process for Management of Systematic Faults
    1. 3.1 TI New-Product Development Process
    2. 3.2 TI Functional Safety Development Process
  5. 4MSPM0Gx51x and MSPM0Gx52x Component Overview
    1. 4.1 Targeted Applications
    2. 4.2 Hardware Component Functional Safety Concept
    3. 4.3 Functional Safety Constraints and Assumptions
  6. 5Description of Hardware Component Parts
    1. 5.1  ADC
    2. 5.2  Comparator
    3. 5.3  DAC
    4. 5.4  CPU
    5. 5.5  RAM
    6. 5.6  FLASH
    7. 5.7  GPIO
    8. 5.8  DMA
    9. 5.9  SPI
    10. 5.10 I2C
    11. 5.11 UART
    12. 5.12 Timers (TIMx)
    13. 5.13 Power Management Unit (PMU)
    14. 5.14 Clock Module (CKM)
    15. 5.15 CAN-FD
    16. 5.16 Events
    17. 5.17 IOMUX
    18. 5.18 VREF
    19. 5.19 WWDT and IWDT
    20. 5.20 CRC
  7. 6MSPM0Gx51x and MSPM0Gx52x Management of Random Faults
    1. 6.1 Fault Reporting
    2. 6.2 Functional Safety Mechanism Categories
    3. 6.3 Description of Functional Safety Mechanisms
      1. 6.3.1  ADC1, COMP1, DAC1, DMA1, GPIO2, TIM2, I2C2, IOMUX1, SPI2, UART2, SYSCTL5, MCAN3, CPU4, CRC1, EVENT1, REF1, WDT1_latent, IWDT1_latent: Periodic Read of Static Configuration Registers
      2. 6.3.2  ADC7: Software Test of Functionality Using External Inputs
      3. 6.3.3  ADC3: ADC Trigger Overflow
      4. 6.3.4  ADC4: Window Comparator
      5. 6.3.5  ADC5_latent: Test of Window Comparator
      6. 6.3.6  ADC6: ADC Trigger, Output Plausibility Checks
      7. 6.3.7  COMP2: Software Test of Comparator Using Internal DAC
      8. 6.3.8  COMP3: External Pin Input to COMP
      9. 6.3.9  COMP4: Comparator Hysteresis
      10. 6.3.10 COMP5: Redundant Comparator
      11. 6.3.11 WDT: Windowed Watchdog Timer
      12. 6.3.12 WDT2_latent: WWDT Counter Check
      13. 6.3.13 WDT3_latent: WWDT Software Test
      14. 6.3.14 WDT4_latent: Redundant WDT
      15. 6.3.15 REF2: VREF to ADC Reference Input
      16. 6.3.16 CPU1: CPU Test Using Software Test Library
      17. 6.3.17 CPU2: Software Test of CPU Data Buses
      18. 6.3.18 CPU3: Software Diversified Redundancy
      19. 6.3.19 SYSMEM1: Software Read of Memory, DMA Write
      20. 6.3.20 SYSMEM2: DMA Read from SRAM, CPU Write
      21. 6.3.21 SYSMEM3_latent: Parity Logic Test
      22. 6.3.22 SYSMEM4: Parity Protection on SRAM
      23. 6.3.23 SYSMEM7: ECC Protection on SRAM
      24. 6.3.24 SYSMEM8_latent: ECC Logic Test
      25. 6.3.25 SYSMEM9: RAM Software Test
      26. 6.3.26 FLASH1: FLASH Single Error Correction, Double Error Detection Mechanism
      27. 6.3.27 FLASH2: Flash CRC
      28. 6.3.28 FXBAR2: Periodic Software Read Back of Flash Data
      29. 6.3.29 FXBAR3_latent: Software Test of ECC Checker Logic
      30. 6.3.30 FXBAR4: Write Protection of Flash
      31. 6.3.31 DAC2: DAC Test Using Internal ADC as DAC Output Checker
      32. 6.3.32 DAC3: DAC FIFO Underrun Interrupt
      33. 6.3.33 DMA2: Software Test of DMA Function
      34. 6.3.34 DMA3: Software DMA Channel Test
      35. 6.3.35 DMA4: CRC Check of the Transferred Data
      36. 6.3.36 GPIO1: GPIO Test Using Pin I/O Loopback
      37. 6.3.37 GPIO3: GPIO Multiple (Redundant) Inputs/Outputs
      38. 6.3.38 TIM1: Test for PWM Generation
      39. 6.3.39 TIM3: Test for Fault Generation
      40. 6.3.40 TIM4: Fault Detection to Take the PWMs to Safe State
      41. 6.3.41 TIM5: Input Capture on Two or More Timer Instances
      42. 6.3.42 TIM6: Timer Period Monitoring
      43. 6.3.43 I2C1: Software Test of I2C Function Using Internal Loopback Mechanism
      44. 6.3.44 I2C3, SPI4, UART3, MCAN2: Information Redundancy Techniques Including End-to-End Safing
      45. 6.3.45 I2C4, SPI5, UART4: Transmission Redundancy
      46. 6.3.46 I2C5, UART5: Timeout Monitoring
      47. 6.3.47 I2C6: Test of CRC Function
      48. 6.3.48 I2C7: Packet Error Check in SMBUS Mode
      49. 6.3.49 IOMUX2: IOMUX Coverage as Part of Other IP Safety Mechanisms
      50. 6.3.50 SPI1: Software Test of SPI Function
      51. 6.3.51 SPI3: SPI Periodic Safety Message Exchange
      52. 6.3.52 UART1: Software Test of UART Function
      53. 6.3.53 UART6: UART Error Flags
      54. 6.3.54 UART7: UART Glitch filter
      55. 6.3.55 SYSCTL1: MCLK Monitor
      56. 6.3.56 SYSCTL2: HFCLK Start-Up Monitor
      57. 6.3.57 SYSCTL3: LFCLK Monitor
      58. 6.3.58 SYSCTL6: SYSPLL Start-Up Monitor
      59. 6.3.59 SYSCTL8: Brownout Reset (BOR) Supervisor
      60. 6.3.60 SYSCTL9: FCC Counter Logic to Calculate Clock Frequencies
      61. 6.3.61 SYSCTL10: External Voltage Monitor
      62. 6.3.62 SYSCTL11: Boot Process Monitor
      63. 6.3.63 SYSCTL14: Brownout Voltage Monitor
      64. 6.3.64 SYSCTL15: External Voltage Monitor
      65. 6.3.65 SYSCTL16: External Watchdog Timer
      66. 6.3.66 MCAN1: Software test of function using I/O Loopback
      67. 6.3.67 MCAN4: SRAM ECC
      68. 6.3.68 MCAN5_latent: Software Test of ECC Check Logic
      69. 6.3.69 MCAN6: MCAN Timeout Function
      70. 6.3.70 MCAN7: MCAN Timestamp Function
      71. 6.3.71 CRC: CRC Checker
      72. 6.3.72 EVENT2: Interrupt Connectivity Check
      73. 6.3.73 Safety Mechanisms Covering PIN Failures
      74. 6.3.74 Safety Mechanisms Covering Common Cause Failures
  8.   A Summary of Recommended Functional Safety Mechanism Usage
  9.   B Distributed Developments
    1.     B.1 How the Functional Safety Lifecycle Applies to TI Functional Safety Products
    2.     B.2 Activities Performed by Texas Instruments
    3.     B.3 Information Provided
  10.   C Internal TI Revision
  11.   D Revision History

6.3.34 DMA3: Software DMA Channel Test

In this method, DMA channels in use are periodically triggered after changing the source address to flash and destination address to SRAM. Known data is transferred from flash to SRAM and the data in SRAM is compared to the data in flash. In addition, a timer can be set up to monitor completion within a reasonable time.