SFFS422 May   2022

 

  1.   Trademarks
  2.   2
  3. 1Scope
  4. 2Related Documents
  5. 3Related Standards and Acronyms
  6. 4Concept Overview
    1. 4.1 System Block Diagram
    2. 4.2 System Specifications
    3. 4.3 Conditions of use: Assumptions
      1. 4.3.1 Generic Assumptions
      2. 4.3.2 Specific Assumptions
    4. 4.4 Safe Torque Off Implementation
      1. 4.4.1 Subsystem Elements
      2. 4.4.2 STO Safe Subsystem States and Timing Diagram
      3. 4.4.3 STO_1 Subsystem
      4. 4.4.4 STO_2 Subsystem
      5. 4.4.5 MCU (SIL 1) Diagnostic Coverage
      6. 4.4.6 STO_FB Subsystem
      7. 4.4.7 Information on ICs
        1. 4.4.7.1 Isolated 24-V Input Receiver
        2. 4.4.7.2 Load Switch: TPS22919
        3. 4.4.7.3 High-Side Switch: TPS27S100
        4. 4.4.7.4 Isolated Gate Driver: ISO5852S (ISO5452)
    5. 4.5 Safe State
  7. 5Concept FMEA
    1. 5.1 System FMEA
  8. 6References

4.1 System Block Diagram

Figure 4-1 shows the overall system block diagram.

Figure 4-1 High-Level System Block Diagram of TIDA-01599 Concept

STO_1 and STO_2 control the primary and secondary side power supply to the six isolated IGBT gate driver through a power switch (VCC) and a high side switch (P24V) respectively. As long as a logic 1 (+24-V DC) is present at both STO inputs, the motor is operable. If there is a logic 0 (0 V) at one or both of the STO inputs, the power supplies to the gate drivers will be disconnected and the motor coasts down to zero. The use of 1oo2 architecture helps achieve HFT = 1 and only the occurrence of two simultaneous faults can cause failure of the safety function.

The MCU (SIL 1) implements the diagnostics coverage of the STO_1 and STO_2 safe subsystems and sets the system to a safe state, when a fault is detected.

An STO_FB signal is provided to indicate the status of the drive (safe state or normal operation) and can be used to feedback the drive’s status to a safety PLC for additional diagnostics, if desired.