SFFS422 May   2022

 

  1.   Trademarks
  2.   2
  3. 1Scope
  4. 2Related Documents
  5. 3Related Standards and Acronyms
  6. 4Concept Overview
    1. 4.1 System Block Diagram
    2. 4.2 System Specifications
    3. 4.3 Conditions of use: Assumptions
      1. 4.3.1 Generic Assumptions
      2. 4.3.2 Specific Assumptions
    4. 4.4 Safe Torque Off Implementation
      1. 4.4.1 Subsystem Elements
      2. 4.4.2 STO Safe Subsystem States and Timing Diagram
      3. 4.4.3 STO_1 Subsystem
      4. 4.4.4 STO_2 Subsystem
      5. 4.4.5 MCU (SIL 1) Diagnostic Coverage
      6. 4.4.6 STO_FB Subsystem
      7. 4.4.7 Information on ICs
        1. 4.4.7.1 Isolated 24-V Input Receiver
        2. 4.4.7.2 Load Switch: TPS22919
        3. 4.4.7.3 High-Side Switch: TPS27S100
        4. 4.4.7.4 Isolated Gate Driver: ISO5852S (ISO5452)
    5. 4.5 Safe State
  7. 5Concept FMEA
    1. 5.1 System FMEA
  8. 6References

4.4.7.4 Isolated Gate Driver: ISO5852S (ISO5452)

GUID-183CD3AA-171A-40A7-AB3E-08C7A5AAF6CD-low.gif Figure 4-11 ISO5852S (ISO5452) Block Diagram

Table 4-6 shows the ISO5852S (ISO5452) isolated gate driver output voltage depending on the logic supply voltage VCC1 and the isolated supply voltage VCC2. If any of these supply voltages is off (see threshold values under footnote 1), the output OUTH/L of the gate driver is low. Table 4-6 is copied from the ISO5852S (ISO5452) data sheet, reference number SLLSEQ0 and SLLSEQ4.

Table 4-6 ISO5852S (ISO5452) Functional Table VCC1 and VCC2/VEE2 vs Output Voltage
GUID-20220331-SS0I-7TVG-QTHT-TDM5KL6KBMPM-low.png