3.11 R_iso With Dual Feedback

Figure 36 shows the schematic for the R_iso with dual-feedback circuit configuration.

The dc gain of the R_iso with dual-feedback circuit configuration can be calculated using Equation 24.

In situations where stability is affected by capacitive loads, the R_iso dual-feedback configuration has the ability to stabilize the circuit by compensating the contribution of the capacitive load to circuit instability. This capacitive load compensation technique uses an isolation resistor that compensates the circuit by adding a zero to cancel the pole from the output impedance and capacitive load. Refer to the TI Precision Labs - Op Amps: Stability 5 video for detailed information on this technique.

The design steps for the R_iso method follow:

1. Use TINA-TI™ to find the zero frequency, f_ZERO, where A_{OL_Loaded} = 20 dB (example shown in Figure 37).
Figure 37. Example of f_ZERO, Where A_{OL_Loaded} = 20 dB
2. Calculate R_iso to set the zero at f_ZERO – this will yield between 60° and 90° of phase margin
Equation 25.
where

• R_iso = R3
• C_Load = C4

While the R_iso circuit is both simple to implement and design, it has a big disadvantage in precision circuits. The voltage drop from R_iso is dependent on the output current or output load, and may be significant compared to the desired signal.

The second capacitive load compensation technique uses the R_iso with dual-feedback stability compensation method. The R_iso dual-feedback circuit solves the voltage drop disadvantage of the previously stated R_iso. Refer to the TI Precision Labs - Op Amps: Stability 6 video for detailed information on this technique.

Design steps for the R_iso method follow:

1. R_iso using Method 1: R_iso techniques
2. Set R1: R₁ ≥ (R_iso × 100)
3. Set C₁:

Using this range ensures that the two feedback paths, R₂ and C₃, will never create a resonance that would cause instability. Smaller values of C3 will result in faster settling time at the expense of overshoot for certain load ranges. While the R_iso dual-feedback circuit solves the dc accuracy issue with the R_iso circuit, it has some disadvantages as well. The disadvantage of this method is that the circuit is not as tolerant to changes in the output capacitance and can quickly become unstable. Therefore, the R_iso dual-feedback circuit is best for situations where the output capacitance is known and will not vary significantly. This method generally results in a slower settling time than the R_iso circuit as well.

The PCB layout of the top layer of the R_iso dual-feedback amplifier circuit configuration is displayed in Figure 38

The PCB layout of the bottom layer of the R_iso dual-feedback amplifier circuit configuration is displayed in Figure 39.