Figure 5-1 shows a block diagram of the test setup used for SEE testing. The inputs to the ADS1282-SP (DIN, SCLK, PWRDN_N, RESET_N, and SYNC) are connected to I/O pins on a Spartan 6 FPGA. The CLK operates at 4MHz and the SCLK operates at 2MHz. The outputs of the ADS1282-SP (DOUT, DRDY_N, MCLK, M1, M0, and MFLAG) are also connected to I/O pins on the FPGA. The FPGA sends commands to the ADS1282-SP and executes reading and writing to ADS1282-SP registers.

Figure 5-2 SEE Testing Block Diagram

The SEE Test Setup for the TI ADS1282-SP is shown in Figure 5-3. Each TI ADS1282-SP is mounted on an individual DUT board that interfaces to the Memory Test Board. The Keithley 2425-C and 2420 Source Meters provide the DUT AVDD and DUT DVDD voltages and measures the associated currents. The Housekeeping Power Supply provides the ±5V and +24V for the Memory Test Board. The Agilent 34970A Data Acquisition Unit and Agilent 34901A Multiplexer Plug-in provide the capability to measure the DUT AVDD, DUT DVDD and 3.3V voltages at the DUT board. The Shutter Status Monitor records the beam shutter position. The laptop personal computer (PC) controls the test equipment and records the test data [6].

Figure 5-3 SEE Test Circuit