SLUS829G August 2008 – February 2020 UCC2897A
PRODUCTION DATA.
The internal 5-V bias rail of the controller is connected to this pin. The internal bias-regulator requires a high-quality ceramic-bypass capacitor (CVREF) to GND for noise filtering and to provide compensation to the regulator circuitry. The recommended CVREF value is 0.22 μF and X7R capacitors are recommended. The minimum-bypass capacitor value is 0.022 μF limited by stability considerations of the bias regulator, while the maximum is approximately 22 μF. The capacitance on VREF and VDD should be in a minimum ratio of 1:10.
The VREF pin is internally current-limited and supplies approximately 5 mA to external circuits. The 5-V bias is available only when the undervoltage lock-out (UVLO) circuit enables the operation of UCC2897A controller. The VREF-bias profile may not be monotonic before VDD reaches 5 V.
For the detailed functional description of the undervoltage lock-out (UVLO) circuit refer to the section of this datasheet.