SLUS168F April   1999  – July 2025 UCC2808-1 , UCC2808-2 , UCC3808-1 , UCC3808-2

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Pin Descriptions
    4. 6.4 Device Functional Modes
      1. 6.4.1 VCC
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Related Links
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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Electrical Characteristics

TA = 0°C to 70°C for the UCC3808-x, –40°C to 85°C for the UCC2808-x and –55°C to 125°C for the UCC1808-x, VDD = 10V(1), 1μF capacitor from VDD to GND, R = 22kΩ, C = 330pF, TA = TJ, (unless otherwise specified)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
OSCILLATOR SECTION
Oscillator frequency175194213kHz
Oscillator amplitude/VDD(2)0.440.50.56V/V
ERROR AMPLIFIER SECTION
Input voltageCOMP = 2V1.9522.05V
Input bias current–11μ A
Open-loop voltage gain6080dB
COMP sink currentFB = 2.2V, COMP = 1V0.32.5mA
COMP source currentFB = 1.3V, COMP = 3.5V–0.25–0.5mA
PWM SECTION
Maximum duty cycleMeasured at OUTA or OUTB48%49%50%
Minimum duty cycleCOMP =0V0%
CURRENT SENSE SECTION
Gain(3)1.92.22.5V/V
Maximum input signalCOMP = 5V(4)0.450.50.55V
CS to output delayCOMP = 3.5V, CS from 0mV to 600mV100200ns
CS source current–200nA
Over current threshold0.70.750.8V
COMP to CS offsetCS = 0V0.350.81.2V
OUTPUT SECTION
OUT low levelI = 100mA0.51V
OUT high levelI = – 50mA, VDD – OUT0.51V
Rise timeCL =1nF2560ns
Fall timeCL = 1nF2560ns
UNDERVOLTAGE LOCKOUT SECTION
Start thresholdUCCx808-1(1)11.512.513.5V
UCCx808-24.14.34.5
Minimum operating voltage after startUCCx808-17.68.39V
UCCx808-23.94.14.3
HysteresisUCCx808-13.54.25.1V
UCCx808-20.10.20.3
SOFT-START SECTION
COMP rise timeFB = 1.8V, rise from 0.5V to4V3.520ms
OVERALL SECTION
Start-up currentVDD < start threshold130260µA
Operating supply currentFB = 0V, CS = 0V (5)(1)12mA
VDD zener shunt voltageIDD = 10mA(6)131415V
Does not include current in the external oscillator network.
Measured at RC. Signal amplitude tracks VDD.
Gain is defined by: Equation 1
Parameter measured at trip point of latch with FB at 0V.
For UCCx808 – 1, set VDD above the start threshold before setting at 10V
Start threshold and Zener shunt threshold track one another.
Equation 1. A = V C O M P V C S , 0 V C S 0.4 V