ZHCSNM5C november   2020  – august 2023 UCC25800-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Management
      2. 8.3.2 Oscillator
      3. 8.3.3 External Synchronization
      4. 8.3.4 Dead-Time
        1. 8.3.4.1 Adaptive Dead-time
        2. 8.3.4.2 Maximum Programmable Dead-time
      5. 8.3.5 Protections
        1. 8.3.5.1 Overcurrent Protection
          1. 8.3.5.1.1 OCP Threshold Setting
          2. 8.3.5.1.2 Output Power Capability
        2. 8.3.5.2 Input Overvoltage Protection (OVP)
        3. 8.3.5.3 Over-Temperature Protection (TSD)
        4. 8.3.5.4 Pin-Fault Protections
        5. 8.3.5.5 VREG Pin Protection
      6. 8.3.6 DIS/FLT Pin operation
        1. 8.3.6.1 FAULT Codes
    4. 8.4 Device Functional Modes
      1. 8.4.1 UVLO Mode
      2. 8.4.2 Soft-start Mode
      3. 8.4.3 Normal Operation Mode
      4. 8.4.4 Disabled Mode
      5. 8.4.5 Fault Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 LLC Converter Operation Principle
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 What to Do and What Not to Do
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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6 Pin Configuration and Functions

GUID-20210719-CA0I-JRJC-SZFF-8L2H9ZJDGHR6-low.svg Figure 6-1 DGN Package, 8-Pin PDSO (Top View)
Table 6-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
DIS/FLT 2 I/O UCC25800-Q1 disable pin (active low) and fault code output pin.
GND 6 G The GND pin is the return for all the control and power signals. The layout should separate the power and control signals.
OC/DT 4 I Voltage on this pin sets the maximum dead-time between the internal switching power devices. The Thevenin resistance on the pin is measured at start-up to set the OCP level.
RT 5 – Switching frequency setting pin. Connect a resistor from RT pin to GND to set the converter switching frequency. The RT pin can be left open to operate the converter at the default 1.2-MHz switching frequency.
SW 7 – The switch node of the integrated half-bridge. Connect this pin directly to the transformer.
SYNC 1 I External clock input for frequency synchronization. The internal MOSFETs are switched synchronized with the rising edge of the SYNC signal, with half of the SYNC pin signal frequency.
VCC 8 I The input for power and control of UCC25800-Q1. A good high-frequency by-pass capacitor between VCC and GND is needed to ensure high-efficiency, low-EMI design. Use the bypass capacitor layout to minimize the VCC-GND-bypass capacitor loop to reduce the stresses on internal power devices. Referring to Section 11 for layout guidelines.
VREG 3 O Internal regulated reference. Put a decoupling capacitor right across VREG pin and GND with shortest distance. The VREG pin can also be used as an external supply.
Thermal Pad – Connect this pad to GND pin to provide thermal management for the device. Thermal vias are recommended if the design uses multilayer PCB.
(1) I = input, O = output, I/O = input or output, FB = feedback, G = ground, P = power