SLUS846C September 2008 – June 2015 UCC25600
PRODUCTION DATA.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)| MIN | MAX | UNIT | |
|---|---|---|---|
| Supply voltage, VCC | 22 | V | |
| Voltage, GD1, GD2 | –0.5 | VCC + 0.5 | V |
| Gate drive current – continuous, GD1, GD2 | ±25 | mA | |
| Current, RT | –5 | mA | |
| Current, DT | –0.7 | mA | |
| Lead temperature (10 seconds) | 260 | °C | |
| Operating junction temperature, TJ | –40 | 125 | °C |
| Storage temperature, Tstg | –65 | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|
| VCC input voltage from a low-impedance source | 11.5 | 18.0 | V | |
| RT resistance | 1 | 8.666 | kΩ | |
| DT resistance | 3.3 | 39 | kΩ | |
| SS capacitor | 0.01 | 1 | μF |
6.4 Thermal Information
| THERMAL METRIC(1) | UCC25600 | UNIT | |
|---|---|---|---|
| D (SOIC) | |||
| 8 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 118.5 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 72.5 | °C/W |
| RθJB | Junction-to-board thermal resistance | 58.9 | °C/W |
| ψJT | Junction-to-top characterization parameter | 24.1 | °C/W |
| ψJB | Junction-to-board characterization parameter | 58.4 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| BIAS SUPPLY (VCC) | ||||||
| VCC current, disabled | SS = 0 V | 1 | 1.5 | mA | ||
| VCC current, enabled | SS = 5 V, CGD1 = CGD2 = 1 nF | 2.5 | 5 | 7.5 | ||
| VCC current, UVLO | VCC = 9 V | 100 | 400 | μA | ||
| VUVLO | UVLO turn-on threshold | Measured at VCC rising | 9.9 | 10.5 | 11.1 | V |
| UVLO turn-off threshold | Measured at VCC falling | 8.9 | 9.5 | 10.1 | ||
| UVLO hysteresis | Measured at VCC | 0.7 | 1 | 1.3 | ||
| VOVP | OVP turn-off threshold | Measured at VCC rising | 18 | 20 | 22 | |
| OVP turn-on threshold | Measured at VCC falling | 16 | 18 | 20 | ||
| OVP hysteresis | Measured at VCC | 1.5 | 2 | 2.5 | ||
| DEAD TIME (DT) | ||||||
| TDT | Dead time | RDT = 16.9 kΩ | 390 | 420 | 450 | ns |
| OSCILLATOR | ||||||
| FSW(min) | Minimum switching frequency at GD1, GD2 | –40°C to 125°C | 40.04 | 41.70 | 43.36 | kHz |
| –20°C to 105°C | 40.45 | 41.70 | 42.95 | |||
| KICO | Switching frequency gain/I (RT) | RRT = 4.7 kΩ, IRT = 0 to 1 mA | 60 | 80 | 100 | Hz/μA |
| GD1, GD2 on time mismatching | –50 | 50 | ns | |||
| FSW_BM | Switching frequency starting burst mode | SS = 5 V | 300 | 350 | 400 | kHz |
| Switching frequency to come out of burst mode | SS = 5 V | 280 | 330 | 380 | ||
| FSW(start) | Switching frequency at soft-start | –40°C to 125°C | 122 | 142.5 | 162 | |
| –20°C to 105°C | 125 | 142.5 | 160 | |||
| EXTERNAL DISABLE/SOFT START | ||||||
| Enable threshold | Measure at SS rising | 1.1 | 1.2 | 1.3 | V | |
| Disable threshold | Measured at SS falling | 0.85 | 1 | 1.1 | ||
| Disable hysteresis | Measured at SS | 0.15 | 0.35 | |||
| Disable prop. delay | Measured between SS (falling) and GD2 (falling) | 250 | 500 | 750 | ns | |
| ISS | Source current on ISS pin | VSS = 0.5 V | –225 | –175 | –125 | μA |
| Source current on ISS pin | VSS = 1.35 V | –5.5 | –5 | –4.5 | ||
| PEAK CURRENT LIMIT | ||||||
| VOC1(off) | Level 1 overcurrent threshold – VOC rising | 0.9 | 1 | 1.1 | V | |
| VOC2(off) | Level 2 overcurrent latch threshold – VOC rising | 1.8 | 2.0 | 2.2 | ||
| VOC1(on) | Level 1 overcurrent threshold – VOC falling | 0.5 | 0.6 | 0.7 | ||
| Td_OC | Propagation delay | 60 | 200 | 500 | ns | |
| IOC | OC bias current | VOC = 0.8 V | –200 | 200 | nA | |
| GATE DRIVE | ||||||
| GD1, GD2 output voltage high | IGD1, IGD2 = −20 mA | 9 | 11 | V | ||
| GD1, GD2 on resistance high | IGD1, IGD2 = −20 mA | 12 | 30 | Ω | ||
| GD1, GD2 output voltage low | IGD1, IGD2 = 20 mA | 0.08 | 0.2 | V | ||
| GD1, GD2 on resistance low | IGD1, IGD2 = 20 mA | 4 | 10 | Ω | ||
| Rise time GDx | 1 V to 9 V, CLOAD = 1 nF | 18 | 35 | ns | ||
| Fall time GDx | 9 V to 1 V, CLOAD = 1 nF | 12 | 25 | |||
| GD1, GD2 output voltage during UVLO | VCC = 6 V, IGD1, IGD2 = 1.2 mA | 0.5 | 1.75 | V | ||
| THERMAL SHUTDOWN | ||||||
| Thermal shutdown threshold | 160 | °C | ||||
| Thermal shutdown recovery threshold | 140 | |||||
6.6 Typical Characteristics
At VCC = 12 V, RRT = 4.7 kΩ, RDT = 16.9 kΩ, VSS = 5 V, VOC = 0 V; all voltages are with respect to GND, TJ = TA = 25°C, unless otherwise noted.
