ZHCSOE5B March   2022  – January 2023 UCC21737-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Switching Characteristics
    10. 6.10 Insulation Characteristics Curves
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay
      1. 7.1.1 Regular Turn-OFF
    2. 7.2 Input Deglitch Filter
    3. 7.3 Active Miller Clamp
      1. 7.3.1 External Active Miller Clamp
    4. 7.4 Undervoltage Lockout (UVLO)
      1. 7.4.1 VCC UVLO
      2. 7.4.2 VDD UVLO
      3. 7.4.3 VEE UVLO
    5. 7.5 Overcurrent (OC) Protection
      1. 7.5.1 OC Protection with Soft Turn-OFF
    6. 7.6 ASC Support
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power Supply
      2. 8.3.2  Driver Stage
      3. 8.3.3  VCC, VDD, and VEE Undervoltage Lockout (UVLO)
      4. 8.3.4  Active Pulldown
      5. 8.3.5  Short Circuit Clamping
      6. 8.3.6  External Active Miller Clamp
      7. 8.3.7  Overcurrent and Short Circuit Protection
      8. 8.3.8  Soft Turn-off
      9. 8.3.9  Fault (FLT), Reset, and Enable (RST/EN)
      10. 8.3.10 ASC Support and APWM Monitor
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Filters for IN+, IN-, and RST/EN
        2. 9.2.2.2 PWM Interlock of IN+ and IN-
        3. 9.2.2.3 FLT, RDY, and RST/EN Pin Circuitry
        4. 9.2.2.4 RST/EN Pin Control
        5. 9.2.2.5 Turnon and Turnoff Gate Resistors
        6. 9.2.2.6 External Active Miller Clamp
        7. 9.2.2.7 Overcurrent and Short Circuit Protection
          1. 9.2.2.7.1 Protection Based on Power Modules with Integrated SenseFET
          2. 9.2.2.7.2 Protection Based on Desaturation Circuit
          3. 9.2.2.7.3 Protection Based on Shunt Resistor in Power Loop
        8. 9.2.2.8 Higher Output Current Using an External Current Buffer
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 第三方产品免责声明
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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6.8 Electrical Characteristics

VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDD–COM = 20 V, 18 V or 15 V, COM–VEE = 5 V, 8 V or 15 V,
CL = 100pF, –40°C<TJ<150°C (unless otherwise noted)(1)(2).
Parameter TEST CONDITIONS MIN TYP MAX UNIT
VCC UVLO THRESHOLD AND DELAY
VVCC_ON VCC - GND 2.55 2.7 2.85 V
VVCC_OFF 2.35 2.5 2.65 V
VVCC_HYS 0.2 V
tVCCFIL VCC UVLO deglitch time   10   µs
tVCC+ to OUT VCC UVLO on delay to output high IN+ = VCC, IN– = GND 28 37.8 55 µs
tVCC- to OUT VCC UVLO off delay to output low 5 10 15 µs
tVCC+ to RDY VCC UVLO on delay to RDY high RST/EN = VCC 30 37.8 55 µs
tVCC- to RDY VCC UVLO off delay to RDY low 5 10 15 µs
VDD UVLO THRESHOLD AND DELAY
VVDD_ON VDD - COM 10.5 11.4 12.8 V
VVDD_OFF 9.9 10.6 11.8 V
VVDD_HYS 0.8 V
tVDDFIL VDD UVLO deglitch time 5 µs
tVDD+ to OUT VDD UVLO on delay to output high IN+ = VCC, IN– = GND 2 5 15 µs
tVDD- to OUT VDD UVLO off delay to output low   5 15 µs
tVDD+ to RDY VDD UVLO on delay to RDY high RST/EN = VCC   10 15 µs
tVDD- to RDY VDD UVLO off delay to RDY low   10 15 µs
VEE UVLO THRESHOLD AND DELAY
VVEE_ON VEE - COM -3.5 -3.1 -2.7 V
VVEE_OFF -3.0 -2.6 -2.2 V
VVEE_HYS   -0.5   V
tVEEFIL VEE UVLO deglitch time   5   µs
tVEE+ to OUT VEE UVLO on delay to output high IN+ = VCC, IN– = GND   8 15 µs
tVEE- to OUT VEE UVLO off delay to output low   5 15 µs
tVEE+ to RDY VEE UVLO on delay to RDY high RST/EN = VCC   10 25 µs
tVEE- to RDY VEE UVLO off delay to RDY low   12 25 µs
VCC, VDD QUIESCENT CURRENT
IVCCQ VCC quiescent current  OUT(H) = High, fS = 0Hz 2.5 3 4 mA
OUT(L) = Low, fS = 0Hz 1.45 2 2.75 mA
IVDDQ VDD quiescent current OUT(H) = High, fS = 0Hz 2.4 3.1 5.3 mA
OUT(L) = Low, fS = 0Hz 2.2 2.9 4.7 mA
IVEEQ VEE quiescent current OUT(H) = High, fS = 0Hz, VEE = -3.5V -830 -630 -430 µA
OUT(L) = Low, fS = 0Hz, VEE = -3.5V -830 -630 -430 µA
LOGIC INPUTS - IN+, IN- and RST/EN
VINH Input high threshold VCC=3.3V   1.85 2.31 V
VINL Input low threshold 0.99 1.52   V
VINHYS Input threshold hysteresis   0.33   V
IIH Input high level input leakage current VIN = VCC 90   uA
IIL Input low level input leakage current VIN = GND   -90 uA
RIND Input pins pull down resistance 55 kΩ
RINU Input pins pull up resistance 55 kΩ
TINFIL IN+, IN– and RST/EN deglitch (ON and OFF) filter time fS = 50kHz 28 40 60 ns
TRSTFIL Deglitch filter time to reset FLT   500 650 800 ns
GATE DRIVER STAGE
IOUTH Peak source current CL = 0.18µF, fS = 1kHz 10 A
IOUTL Peak sink current   10   A
ROUTH(3) Output pull-up resistance IOUTH = -0.1A 2.5 Ω
ROUTL Output pull-down resistance IOUTL = 0.1A 0.3 Ω
VOUTH High level output voltage IOUTH = -0.2A, VDD = 18V 17.5 V
VOUTL Low level output voltage IOUTL= 0.2A   60 mV
ACTIVE PULLDOWN
VOUTPD Output active pull down on OUTL IOUTL(typ) = 0.1×IOUTL(typ),
VDD=OPEN, VEE=COM		 1.5 2.0 2.5 V
EXTERNAL ACTIVE MILLER CLAMP
VCLMPTH Miller clamp threshold voltage Reference to VEE 1.5 2.0 2.5 V
VCLMPE Output high voltage 4.8 5 5.3 V
ICLMPEH Peak source current CCLMPE = 10nF 0.12 0.25 A
ICLMPEL Peak sink current 0.12 0.25 0.37 A
tCLMPER Rising time CCLMPE = 330pF 20 40 ns
tDCLMPE Miller clamp ON delay time   40 70 ns
SHORT CIRCUIT CLAMPING
VCLP-OUT(H) VOUTH–VDD OUT = High, IOUT(H) = 500mA, tCLP=10µs 0.9 V
VCLP-OUT(L) VOUTL–VDD OUT = High, IOUT(L) = 500mA, tCLP=10µs 1.8 V
OC PROTECTION
IDCHG OC pull down current VOC = 1V 40 mA
VOCTH Detection threshold 0.63 0.7 0.77 V
VOCL Voltage when OUTL = Low Reference to COM, IOC = 5mA 0.13 V
tOCFIL OC fault deglitch filter 95 120 180 ns
tOCOFF OC propagation delay to OUTL 90% 150 270 400 ns
tOCFLT OC to FLT low delay 300 530 750 ns
INTERNAL SOFT TURN OFF
ISTO Soft turn-off current on fault condition VDD-VEE = 20 V, OUTL = 8 V 500 900 1200 mA
ACTIVE SHORT CIRCUIT (ASC)
VASCL ASC input low threshold 1.35 1.5 1.71 V
VASCH ASC input high threshold 2.7 2.9 3.17 V
tASC_r ASC to output rising edge delay 390 660 1120 ns
tASC_f ASC to output falling edge delay 152 300 477 ns
APWM Monitor
fAPWM APWM output frequency VASC=2.5V 360 400 440 kHz
DAPWM APWM duty cycle VASC=0.6V 9 11.5 13.5 %
VASC=2.5V 48.5 50 51.5 %
VASC=4.5V 87.5 90 92.5 %
FLT AND RDY REPORTING
tRDYHLD VDD UVLO RDY low minimum holding time 0.55 1 ms
tFLTMUTE Output mute time on fault Reset fault through RST/EN 0.55 1 ms
RODON Open drain output on resistance IODON = 5mA 30 Ω
VODL Open drain low output voltage   0.3 V
COMMON MODE TRANSIENT IMMUNITY
CMTI Common-mode transient immunity 150     V/ns
(1) Currents are positive into and negative out of the specified terminal.
(2)
All voltages are referenced to COM unless otherwise notified.


(3) For internal PMOS only.  Refer to Driver Stage for effective pull-up resistance.