ZHCSJI6 March 2019 TPS65653-Q1
PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.
Address: 0x20
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
PGOOD_INT_MASK | Reserved | SYNC_CLK
_MASK |
Reserved | TDIE_WARN
_MASK |
Reserved | I_LOAD_
READY_MASK |
Bits | Field | Type | Default | Description |
---|---|---|---|---|
7 | PGOOD_INT
_MASK |
R/W | X | Masking for Power-Good interrupt (PGOOD_INT in INT_TOP_1 register):
0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect PGOOD_STAT status bit in TOP_STAT register. |
6:5 | Reserved | R/W | 00 | |
4 | SYNC_CLK
_MASK |
R/W | X | Masking for external clock detection interrupt (SYNC_CLK_INT in INT_TOP_1 register):
0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect SYNC_CLK_STAT status bit in TOP_STAT register. |
3 | Reserved | R/W | 0 | |
2 | TDIE_WARN
_MASK |
R/W | X | Masking for thermal warning interrupt (TDIE_WARN_INT in INT_TOP_1 register):
0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect TDIE_WARN_STAT status bit in TOP_STAT register. |
1 | Reserved | R/W | 0 | |
0 | I_MEAS
_MASK |
R/W | X | Masking for load current measurement ready interrupt (MEAS_INT in INT_TOP_1 register).
0 - Interrupt generated 1 - Interrupt not generated. |