ZHCSJI6 March 2019 TPS65653-Q1
PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.
Address: 0x1A
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
Reserved | RESET_REG_INT |
Bits | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | Reserved | R/W | 000 0000 | |
0 | RESET_REG_INT | R/W | 0 | Latched status bit indicating that either VANA supply voltage has been below undervoltage threshold level or the host has requested a reset using SW_RESET bit in RESET register. The regulators have been disabled, and registers are reset to default values and the normal startup procedure is done.
Write 1 to clear interrupt. |