ZHCSJI6 March 2019 TPS65653-Q1
PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.
The TPS65653-Q1 device contains a CLKIN input to synchronize the switching clock of the buck regulators with the external clock. The block diagram of the clocking and PLL module is shown in Figure 7. Depending on the EN_PLL bit in PLL_CTRL register and the external clock availability, the external clock is selected and interrupt is generated as shown in Table 2. The interrupt can be masked with SYNC_CLK_MASK bit in TOP_MASK_1 register. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[4:0] bits in PLL_CTRL register, and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must be inside accuracy limits (–10%/+10%) of the selected frequency for valid clock detection.
The SYNC_CLK_INT interrupt in INT_TOP_1 register is also generated in cases where the external clock is expected but it is not available. These cases are start-up (read OTP-to-standby transition) when EN_PLL is 1 and Buck regulator enable (standby-to-active transition) when EN_PLL is 1.
DEVICE OPERATION MODE | EN_PLL | PLL AND CLOCK DETECTOR STATE | INTERRUPT FOR EXTERNAL CLOCK | CLOCK |
---|---|---|---|---|
STANDBY | 0 | Disabled | No | Internal RC |
ACTIVE | 0 | Disabled | No | Internal RC |
STANDBY | 1 | Enabled | When external clock appears or disappears | Automatic change to external clock when available |
ACTIVE | 1 | Enabled | When external clock appears or disappears | Automatic change to external clock when available |