ZHCSJI6 March 2019 TPS65653-Q1
PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.
Address: 0x14
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
Reserved | EN_PLL | Reserved | EXT_CLK_FREQ[4:0] |
Bits | Field | Type | Default | Description |
---|---|---|---|---|
7 | Reserved | R/W | 0 | |
6 | EN_PLL | R/W | X | Selection of external clock and PLL operation:
0 - Forced to internal RC oscillator. PLL disabled. 1 - PLL is enabled in STANDBY and ACTIVE modes. Automatic external clock use when available, interrupt generated if external clock appears or disappears. |
5 | Reserved | R/W | 0 | This bit must be set to '0'. |
4:0 | EXT_CLK_FREQ[4:0] | R/W | X | Frequency of the external clock (CLKIN):
0x00 - 1 MHz 0x01 - 2 MHz 0x02 - 3 MHz ... 0x16 - 23 MHz 0x17 - 24 MHz 0x18...0x1F - Reserved See electrical specification for input clock frequency tolerance. |