ZHCSJI6 March   2019 TPS65653-Q1

PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.  

  1. 1 特性
    1.     简化原理图
  2. 2 应用
  3. 3 说明
    1.     直流/直流效率与输出电流
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Transition Between PWM and PFM Modes
        3. 7.3.1.3 Buck Converter Load Current Measurement
        4. 7.3.1.4 Spread-Spectrum Mode
      2. 7.3.2 Sync Clock Functionality
      3. 7.3.3 Power-Up
      4. 7.3.4 Regulator Control
        1. 7.3.4.1 Enabling and Disabling Regulators
        2. 7.3.4.2 Changing Output Voltage
      5. 7.3.5 Enable and Disable Sequences
      6. 7.3.6 Device Reset Scenarios
      7. 7.3.7 Diagnosis and Protection Features
        1. 7.3.7.1 Power-Good Information (PGOOD pin)
          1. 7.3.7.1.1 PGOOD Pin Gated mode
          2. 7.3.7.1.2 PGOOD Pin Continuous Mode
        2. 7.3.7.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.7.2.1 Output Power Limit
          2. 7.3.7.2.2 Thermal Warning
        3. 7.3.7.3 Protection (Regulator Disable)
          1. 7.3.7.3.1 Short-Circuit and Overload Protection
          2. 7.3.7.3.2 Overvoltage Protection
          3. 7.3.7.3.3 Thermal Shutdown
        4. 7.3.7.4 Fault (Power Down)
          1. 7.3.7.4.1 Undervoltage Lockout
      8. 7.3.8 Operation of the GPO Signals
      9. 7.3.9 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  DEV_REV
        2. 7.6.1.2  OTP_REV
        3. 7.6.1.3  BUCK0_CTRL_1
        4. 7.6.1.4  BUCK0_CTRL_2
        5. 7.6.1.5  BUCK1_CTRL_1
        6. 7.6.1.6  BUCK1_CTRL_2
        7. 7.6.1.7  BUCK0_VOUT
        8. 7.6.1.8  BUCK1_VOUT
        9. 7.6.1.9  BUCK0_DELAY
        10. 7.6.1.10 BUCK1_DELAY
        11. 7.6.1.11 GPO_DELAY
        12. 7.6.1.12 GPO2_DELAY
        13. 7.6.1.13 GPO_CTRL
        14. 7.6.1.14 CONFIG
        15. 7.6.1.15 PLL_CTRL
        16. 7.6.1.16 PGOOD_CTRL_1
        17. 7.6.1.17 PGOOD_CTRL_2
        18. 7.6.1.18 PG_FAULT
        19. 7.6.1.19 RESET
        20. 7.6.1.20 INT_TOP_1
        21. 7.6.1.21 INT_TOP_2
        22. 7.6.1.22 INT_BUCK
        23. 7.6.1.23 TOP_STAT
        24. 7.6.1.24 BUCK_STAT
        25. 7.6.1.25 TOP_MASK_1
        26. 7.6.1.26 TOP_MASK_2
        27. 7.6.1.27 BUCK_MASK
        28. 7.6.1.28 SEL_I_LOAD
        29. 7.6.1.29 I_LOAD_2
        30. 7.6.1.30 I_LOAD_1
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方产品免责声明
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx,VVOUT_Bx, and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V, unless otherwise noted.(1)(2).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EXTERNAL COMPONENTS
CIN_VANA Input filtering capacitance for VANA Effective capacitance, connected from VANA to AGND 100 nF
CIN_BUCK Input filtering capacitance for buck regulators Effective capacitance, connected from VIN_Bx to PGND_Bx 1.9 10 µF
COUT_BUCK Output filtering capacitance for buck regulators, local Effective capacitance 10 22 µF
CPOL_BUCK Point-of-load (POL) capacitance for buck regulators POL capacitance 22 µF
COUT-TOTAL_BUCK Buck output capacitance, total (local and POL) Total output capacitance, VIN_Bx ≤ 4 V and Slew rate ≤ 3.8 mV/µs 150 µF
Total output capacitance, VIN_Bx > 4 V 100 µF
Total output capacitance, Slew rate > 3.8 mV/µs 100 µF
ESRC Input and output capacitor ESR [1-10] MHz 2 10 mΩ
L Inductor Inductance of the inductor 0.47 µH
–30% 30%
DCRL Inductor DCR 25 mΩ
BUCK REGULATORS
V(VIN_Bx), V(VANA) Input voltage range VIN_Bx and VANA pins must be connected to the same supply line 2.8 3.3 5.5 V
VOUT_Bx Output voltage Programmable voltage range 1 1 3.36 V
Step size, 1 V ≤ VOUT < 1.4 V 5 mV
Step size, 1.4 V ≤ VOUT ≤ 3.36 V 20
IOUT_Bx Output current Output current 3(3) A
Input and Output voltage difference Minimum voltage between V(VIN_Bx) and VOUT to fulfill the electrical characteristics 0.8 V
VOUT_Bx_DC DC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperature Force PWM mode –2% 2%
PFM mode. Average output voltage level is increased by max. 20 mV –2% 2% + 20 mV
Ripple voltage PWM mode, L = 0.47 µH, IOUT = 500 mA, COUT = 22uF + 22uF (GCM31CR71A226KE02) 4 mVp-p
PFM mode, L = 0.47 µH, IOUT = 10 mA, COUT = 22uF + 22uF (GCM31CR71A226KE02) 25
DCLNR DC line regulation IOUT = 1 A ±0.05 %/V
DCLDR DC load regulation in PWM mode VOUT_Bx = 1 V, IOUT from 0 to IOUT(max) 0.3%
TLDSR Transient load step response IOUT = 0 A to 3 A, TR = TF = 1 µs, PWM mode, VVIN_Bx = 3.3 V, VOUT_Bx = 1 V, COUT = 44 µF, L = 0.47 µH, fSW = 4 MHz ±60 mV
TLNSR Transient line response V(VIN_Bx) stepping 3 V ↔ 3.5 V, TR = TF = 10 µs, IOUT = IOUT(max) ±10 mV
ILIM FWD Forward current limit per phase (peak for every switching cycle) Programmable range 1.5 4 A
Step size 0.5
Accuracy, V(VIN_Bx) ≥ 3 V, ILIM = 4 A –5% 7.5% 20%
Accuracy, 2.8 V ≤ V(VIN_Bx) < 3 V, ILIM = 4 A –20% 7.5% 20%
ILIM NEG Negative current limit 1.6 2.0 3.0 A
RDS(ON) HS FET On-resistance, high-side FET Between VIN_Bx and SW_Bx pins (I = 1 A) 50 110 mΩ
RDS(ON) LS FET On-resistance, low-side FET Between SW_Bx and PGND_Bx pins (I = 1 A) 45 90 mΩ
ƒSW Switching frequency PWM mode 3.6 4 4.4 MHz
Start-up time (soft start) From ENx to VOUT_Bx = 0.35 V (slew-rate control begins) 120 µs
Output voltage slew-rate(4) SLEW_RATEx[2:0] = 010 –15% 10 15% mV/µs
SLEW_RATEx[2:0] = 011 7.5
SLEW_RATEx[2:0] = 100 3.8
SLEW_RATEx[2:0] = 101 1.9
SLEW_RATEx[2:0] = 110 0.94
SLEW_RATEx[2:0] = 111 0.47
IPFM-PWM PFM-to-PWM - current threshold(5) 550 mA
IPWM-PFM PWM-to-PFM - current threshold(5) 290 mA
RDIS_Bx Output pulldown resistance Regulator disabled 150 250 350 Ω
Output voltage monitoring for PGOOD pin and for power-good Interrupt V(VIN_Bx) and V(VANA) fixed 3.7 V
Overvoltage threshold (compared to DC output voltage level, VVOUT_Bx_DC) 39 50 64 mV
Undervoltage threshold (compared to DC output voltage level, VVOUT_Bx_DC) –53 –40 –29
Deglitch time during operation and after voltage change 4 15 µs
Gating time for PGOOD signal after regulator enable or voltage change PGOOD_MODE = 0 800 µs
EXTERNAL CLOCK AND PLL
fEXT_CLK External input clock(6) Nominal frequency 1 24 MHz
Nominal frequency step size 1
Required accuracy from nominal frequency –10% 10%
External clock detection Delay for missing clock detection 1.8 µs
Delay and debounce for clock detection 20
Clock change delay (internal to external) Delay from valid clock detection to use of external clock 600 µs
PLL output clock jitter Cycle to cycle 300 ps, p-p
PROTECTION FUNCTIONS
Thermal warning(7) Temperature rising, TDIE_WARN_LEVEL = 0 115 125 135 °C
Temperature rising, TDIE_WARN_LEVEL = 1 127 137 147
Hysteresis 20
Thermal shutdown(7) Temperature rising 140 150 160 °C
Hysteresis 20
VANAOVP VANA overvoltage Voltage rising 5.6 5.8 6.1 V
Voltage falling 5.45 5.73 5.96
Hysteresis 40 mV
VANAUVLO VANA undervoltage lockout Voltage rising 2.51 2.63 2.75 V
Voltage falling 2.5 2.6 2.7
Buck short-circuit detection Threshold 280 360 440 mV
LOAD CURRENT MEASUREMENT FOR BUCK REGULATORS
Current measurement range Maximum code 10.22 A
Resolution LSB 20 mA
Measurement accuracy IOUT > 1 A <10%
Measurement time PFM mode (automatically changing to PWM mode for the measurement) 45 µs
PWM mode 4
CURRENT CONSUMPTION
Standby current consumption, regulators disabled 9 µA
Active current consumption, one buck regulator enabled in auto mode, internal RC oscillator, PGOOD monitoring enabled IOUT_Bx = 0 mA, not switching 58 µA
Active current consumption, two buck regulators enabled in auto mode, internal RC oscillator, PGOOD monitoring enabled IOUT_Bx = 0 mA, not switching 100 µA
Active current consumption during PWM operation, one buck regulator enabled IOUT_Bx = 0 mA 15 mA
Active current consumption during PWM operation, two buck regulators enabled IOUT_Bx = 0 mA 30 mA
PLL and clock detector current consumption fEXT_CLK = 1 MHz, Additional current consumption when enabled 2 mA
DIGITAL INPUT SIGNALS EN, SCL, SDA, CLKIN
VIL Input low level 0.4 V
VIH Input high level 1.2
VHYS Hysteresis of Schmitt Trigger inputs 10 80 200 mV
EN/CLKIN pulldown resistance EN_PD/CLKIN_PD = 1 500 kΩ
DIGITAL OUTPUT SIGNALS nINT, SDA
VOL Output low level nINT: ISOURCE = 2 mA 0.4 V
SDA: ISOURCE = 20 mA 0.4 V
RP External pullup resistor for nINT To VIO Supply 10 kΩ
DIGITAL OUTPUT SIGNALS PGOOD, GPO, GPO2
VOL Output low level ISOURCE = 2 mA 0.4 V
VOH Output high level, configured to push-pull ISINK = 2 mA VVANA – 0.4 VVANA V
VPU Supply voltage for external pullup resistor, configured to open-drain VVANA V
RPU External pullup resistor, configured to open-drain 10 kΩ
ALL DIGITAL INPUTS
ILEAK Input current All logic inputs over pin voltage range −1 1 µA
(1) All voltage values are with respect to network ground.
(2) Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified, but do represent the most likely norm.
(3) The maximum output current can be limited by the forward current limit ILIM FWD. The power dissipation inside the die increases the junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient temperature.
(4) The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current.
(5) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage and the inductor current level.
(6) The external clock frequency must be selected so that buck switching frequency is above 1.7 MHz.
(7) For a given device thermal warning will always happen at a lower temperature than thermal shutdown.