SLVSBD1B December   2012  – August 2025 TPS65175

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configurations
  6. 5 Ordering Information #GUID-A66BA10C-7D19-4133-842F-4CC0C2AD52C6/SLVSAP8211
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Thermal Information
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 I2C Interface Timing Characteristics #GUID-79B32470-0E13-4B06-925C-21E3D7AB5A31/SLVSAE57133
    6. 6.6 I2C Timing Diagrams
    7.     14
    8.     15
    9.     16
    10. 6.7 Typical Characteristics
  8. 7 DAC Range Summary
    1.     19
    2. 7.1 Sequencing
    3. 7.2 Power-Up
    4. 7.3 Power-Down
  9. 8 Detailed Description
    1. 8.1  Boost Converter (VDD)
      1. 8.1.1 Enable Signal (DLY2)
      2. 8.1.2 Boost Converter Operation
      3. 8.1.3 Startup (Boost Converter)
      4. 8.1.4 Protections (Boost Converter)
      5. 8.1.5 Setting the Output Voltage VDD
    2. 8.2  Boost Converter Design Procedure
      1. 8.2.1 Inductor Selection (Boost Converter)
      2. 8.2.2 Rectifier Diode Selection (Boost Converter)
      3. 8.2.3 Compensation (COMP)
      4. 8.2.4 Input Capacitor Selection
      5. 8.2.5 Output Capacitor Selection
      6. 8.2.6 DCM Mode
    3. 8.3  Buck Converter (VCC)
      1. 8.3.1 Enable Signal (UVLO)
      2. 8.3.2 Buck converter Operation
      3. 8.3.3 Startup and Short Circuit Protection (Buck Converter)
      4. 8.3.4 Setting the Output Voltage VCC
    4. 8.4  Buck Converter Design Procedure
      1. 8.4.1 Inductor Selection (Buck Converter)
      2. 8.4.2 Rectifier Diode Selection (Buck Converter)
      3. 8.4.3 Input Capacitor Selection (Buck Converter)
      4. 8.4.4 Output Capacitor Selection (Buck Converter)
      5. 8.4.5 DCM Mode
    5. 8.5  Synchronous Buck Converter (HVDD)
      1. 8.5.1 Enable Signal (DLY2)
      2. 8.5.2 Startup and Short Circuit Protection (Synchronous Buck Converter)
      3. 8.5.3 Setting the output voltage HVDD
    6. 8.6  Synchronous Buck Converter Design Procedure
      1. 8.6.1 Inductor Selection (Synchronous Buck Converter)
      2. 8.6.2 Input Capacitor Selection
      3. 8.6.3 Output Capacitor Selection
    7. 8.7  Positive Charge Pump Controller (VGH) and Temperature Compensation
      1. 8.7.1 Enable Signal (DLY3)
      2. 8.7.2 Positive Charge Pump Controller Operation
    8. 8.8  Positive Charge Pump Design Procedure
      1. 8.8.1 Diodes selection (CPP)
      2. 8.8.2 Capacitors Selection (CPP)
      3. 8.8.3 Selecting the PNP Transistor (CPP)
      4. 8.8.4 Positive Charge Pump Protection
    9. 8.9  VGH Temperature Compensation
      1. 8.9.1 Setting the output voltage VGH_LT and VGH_HT
    10. 8.10 Negative Charge Pump (VGL)
      1. 8.10.1 Enable Signal (DLY1)
      2. 8.10.2 Setting the output voltage VGL
    11. 8.11 Negative Charge Pump Design Procedure
      1. 8.11.1 Diodes Selection (CPN)
      2. 8.11.2 Capacitors selection (CPN)
      3. 8.11.3 Selecting the NPN Transistor (CPN)
      4. 8.11.4 Negative Charge Pump Protection
    12. 8.12 P-Vcom Voltage and Gain (VCOM)
      1. 8.12.1 Enable Signal (DLY2)
    13. 8.13 P-Vcom Design Procedure
      1. 8.13.1 Setting the P-Vcom gain
    14. 8.14 P-Vcom Temperature Compensation
      1. 8.14.1 Setting the VCOM output voltage
    15. 8.15 Gamma Buffer (GMA1-GMA6)
      1. 8.15.1 Enable Signal (DLY2)
      2. 8.15.2 Setting the output voltage of GMA1-GMA6
      3. 8.15.3 Output Load (Gamma Buffer)
    16. 8.16 Level Shifters
    17. 8.17 State Machine
    18. 8.18 GCLK
    19. 8.19 MCLK
    20. 8.20 GST
    21. 8.21 E/O
    22. 8.22 Reverse
    23. 8.23 VGH_F and VGH_R
    24. 8.24 VST
    25. 8.25 RESET
    26. 8.26 EVEN and ODD
    27. 8.27 Abnormal Operation
    28. 8.28 CLK1 to CLK6
    29. 8.29 Gate Voltage Shaping
    30. 8.30 Power Supply Sequencing (CLK1-CLK6, VST, RESET)
    31. 8.31 Power Supply Sequencing (EVEN, ODD)
    32. 8.32 Power Supply Sequencing (VGH_F, VGH_R)
    33.     101
    34. 8.33 Typical Applications
  10. 9 APPENDIX – I2C INTERFACE
    1. 9.1 I2C Serial Interface Description
  11. 10Detailed Description
    1. 10.1 DAC Settings
    2. 10.2 I2C Interface Protocol
    3. 10.3 Temperature Compensation
    4. 10.4 PCB Layout Recommendations
  12. 11Register Map
  13. 12DAC Registers
  14. 13Electrostatic Discharge Caution
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Package Option Addendum
      1. 15.1.1 Packaging Information
      2. 15.1.2 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

4 Pin Configurations

TPS65175 TPS65175A
TPS65175 TPS65175A
Table 4-1 Pin Descriptions
PIN I/O1 DESCRIPTION
NAME NO.
REVERSE 1 I REVERSE input pin
GCLK 2 I GCLK input pin
MCLK 3 I MCLK input pin
GST 4 I GST input pin
E/O 5 I E/O input pin
GND 6 Ground pin
VGL 7 I Negative charge pump (VGL) output voltage sense pin
SWN 8 I/O Negative charge pump (VGL) switch pin
CTRLN 9 O Negative charge pump (VGL) base drive signal pin
RST 10 O Reset generator open drain output pin
OUTB 11 I Buck converter (VCC) output voltage sense pin
SWB 12 I/O Buck converter (VCC) switch pin
AGND 13, exposed pad Analog ground pin. Connect this pin to the PowerPAD™.
PVINB 14 I Buck converter (VCC) input supply pin
AVIN 15 I Internal regulator supply pin
PVINH 16 I Synchronous buck converter (HVDD) power input pin
SWH 17 I/O Synchronous buck converter (HVDD) switch pin
OUTH 18 I Synchronous buck converter (HVDD) output voltage sense pin
PGNDH 19 Synchronous buck converter (HVDD) power ground pin
SCL 20 I/O I2C clock pin
SDA 21 I/O I2C data pin
VL 22 O Internal regulator output pin. Connect an output capacitor to this pin
TCOMP 23 I Temperature compensation input pin. Connect the thermistor / pull-up resistor network to this pin
PGND 24 Boost converter (VDD) power ground pin
SW 25,26 I/O Boost converter (VDD) switch pin
SWI 27 I Isolation switch input pin. The SWI pin is connected to the internal overvoltage protection comparator of the boost converter
SWO 28 O Isolation switch output pin (VDD)
SS 29 O Boost converter (VDD) soft-start pin. Connect a capacitor to this pin if a soft-start is needed. Open = no soft-start.
COMP 30 I/O Boost converter (VDD) compensation pin
GMA1 31 O Gamma buffer 1 output pin. DAC output
GMA2 32 O Gamma buffer 2 output pin. DAC output
GMA3 33 O Gamma buffer 3 output pin. DAC output
GMA4 34 O Gamma buffer 4 output pin. DAC output
GMA5 35 O Gamma buffer 5 output pin. DAC output
GMA6 36 O Gamma buffer 6 output pin. DAC output
VGND 37 Ground pin for the VCOM Op-Amp
VCOM 38 O Operational amplifier (VCOM) output pin
VCOM_FB 39 I Operational amplifier (VCOM) inverting pin. Connect the panel feedback to this pin
CTRLP 40 O Positive charge pump (VGH) base drive signal pin
SWP 41 I/O Positive charge pump (VGH) switch pin
VGH 42 I Positive charge pump (VGH) output voltage sense pin and level shifters supply pin
VGH_E/O 43 I EVEN / ODD channels supply pin
RESET 44 O RESET output pin
VST 45 O VST output pin
EVEN 46 O EVEN output pin
ODD 47 O ODD output pin
VGH_F 48 O VGH_F output pin
VGH_R 49 O VGH_R output pin
CLK6 50 O CLK6 output pin
CLK5 51 O CLK5 output pin
CLK4 52 O CLK4 output pin
CLK3 53 O CLK3 output pin
CLK2 54 O CLK2 output pin
CLK1 55 O CLK1 output pin
RE 56 O Gate shaping resistor connection pin
Table 4-2 TPS65175A Pin Descriptions
PIN I/O1 DESCRIPTION2
NAME NO.
N.C 26 Not connected
  1. I = input, O = output
  2. All other pins functions are the same for TPS65175 and TPS65175A.