SLVSBD1B December   2012  – August 2025 TPS65175

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configurations
  6. Ordering Information #GUID-A66BA10C-7D19-4133-842F-4CC0C2AD52C6/SLVSAP8211
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Thermal Information
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 I2C Interface Timing Characteristics #GUID-79B32470-0E13-4B06-925C-21E3D7AB5A31/SLVSAE57133
    6. 6.6 I2C Timing Diagrams
    7.     14
    8.     15
    9.     16
    10. 6.7 Typical Characteristics
  8. DAC Range Summary
    1.     19
    2. 7.1 Sequencing
    3. 7.2 Power-Up
    4. 7.3 Power-Down
  9. Detailed Description
    1. 8.1  Boost Converter (VDD)
      1. 8.1.1 Enable Signal (DLY2)
      2. 8.1.2 Boost Converter Operation
      3. 8.1.3 Startup (Boost Converter)
      4. 8.1.4 Protections (Boost Converter)
      5. 8.1.5 Setting the Output Voltage VDD
    2. 8.2  Boost Converter Design Procedure
      1. 8.2.1 Inductor Selection (Boost Converter)
      2. 8.2.2 Rectifier Diode Selection (Boost Converter)
      3. 8.2.3 Compensation (COMP)
      4. 8.2.4 Input Capacitor Selection
      5. 8.2.5 Output Capacitor Selection
      6. 8.2.6 DCM Mode
    3. 8.3  Buck Converter (VCC)
      1. 8.3.1 Enable Signal (UVLO)
      2. 8.3.2 Buck converter Operation
      3. 8.3.3 Startup and Short Circuit Protection (Buck Converter)
      4. 8.3.4 Setting the Output Voltage VCC
    4. 8.4  Buck Converter Design Procedure
      1. 8.4.1 Inductor Selection (Buck Converter)
      2. 8.4.2 Rectifier Diode Selection (Buck Converter)
      3. 8.4.3 Input Capacitor Selection (Buck Converter)
      4. 8.4.4 Output Capacitor Selection (Buck Converter)
      5. 8.4.5 DCM Mode
    5. 8.5  Synchronous Buck Converter (HVDD)
      1. 8.5.1 Enable Signal (DLY2)
      2. 8.5.2 Startup and Short Circuit Protection (Synchronous Buck Converter)
      3. 8.5.3 Setting the output voltage HVDD
    6. 8.6  Synchronous Buck Converter Design Procedure
      1. 8.6.1 Inductor Selection (Synchronous Buck Converter)
      2. 8.6.2 Input Capacitor Selection
      3. 8.6.3 Output Capacitor Selection
    7. 8.7  Positive Charge Pump Controller (VGH) and Temperature Compensation
      1. 8.7.1 Enable Signal (DLY3)
      2. 8.7.2 Positive Charge Pump Controller Operation
    8. 8.8  Positive Charge Pump Design Procedure
      1. 8.8.1 Diodes selection (CPP)
      2. 8.8.2 Capacitors Selection (CPP)
      3. 8.8.3 Selecting the PNP Transistor (CPP)
      4. 8.8.4 Positive Charge Pump Protection
    9. 8.9  VGH Temperature Compensation
      1. 8.9.1 Setting the output voltage VGH_LT and VGH_HT
    10. 8.10 Negative Charge Pump (VGL)
      1. 8.10.1 Enable Signal (DLY1)
      2. 8.10.2 Setting the output voltage VGL
    11. 8.11 Negative Charge Pump Design Procedure
      1. 8.11.1 Diodes Selection (CPN)
      2. 8.11.2 Capacitors selection (CPN)
      3. 8.11.3 Selecting the NPN Transistor (CPN)
      4. 8.11.4 Negative Charge Pump Protection
    12. 8.12 P-Vcom Voltage and Gain (VCOM)
      1. 8.12.1 Enable Signal (DLY2)
    13. 8.13 P-Vcom Design Procedure
      1. 8.13.1 Setting the P-Vcom gain
    14. 8.14 P-Vcom Temperature Compensation
      1. 8.14.1 Setting the VCOM output voltage
    15. 8.15 Gamma Buffer (GMA1-GMA6)
      1. 8.15.1 Enable Signal (DLY2)
      2. 8.15.2 Setting the output voltage of GMA1-GMA6
      3. 8.15.3 Output Load (Gamma Buffer)
    16. 8.16 Level Shifters
    17. 8.17 State Machine
    18. 8.18 GCLK
    19. 8.19 MCLK
    20. 8.20 GST
    21. 8.21 E/O
    22. 8.22 Reverse
    23. 8.23 VGH_F and VGH_R
    24. 8.24 VST
    25. 8.25 RESET
    26. 8.26 EVEN and ODD
    27. 8.27 Abnormal Operation
    28. 8.28 CLK1 to CLK6
    29. 8.29 Gate Voltage Shaping
    30. 8.30 Power Supply Sequencing (CLK1-CLK6, VST, RESET)
    31. 8.31 Power Supply Sequencing (EVEN, ODD)
    32. 8.32 Power Supply Sequencing (VGH_F, VGH_R)
    33.     101
    34. 8.33 Typical Applications
  10. APPENDIX – I2C INTERFACE
    1. 9.1 I2C Serial Interface Description
  11. 10Detailed Description
    1. 10.1 DAC Settings
    2. 10.2 I2C Interface Protocol
    3. 10.3 Temperature Compensation
    4. 10.4 PCB Layout Recommendations
  12. 11Register Map
  13. 12DAC Registers
  14. 13Electrostatic Discharge Caution
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Package Option Addendum
      1. 15.1.1 Packaging Information
      2. 15.1.2 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

Register Map

The TPS65175/A has one non-volatile memory which contains the initial value of the DAC and one volatile memory which contains the DAC setting. The non-volatile memory is called the Initial Value Register (IVR) and the volatile memory is called DAC Register (DR). The non-volatile IVR and the volatile DR are accessed with the same address.

Startup option: At power-up, the value contained in the IVR is loaded into the volatile DR and IVR presets the DAC to the last stored setting. The factory programmed value of the IVR of each address is described on Table 8-2 and, at power-up, these data byte set the output voltage of each rail.

Write description: The user has to program all data registers first (00h ~ 18h), then set the WED (Write EEPROM Data) bit to 1 once all desired data are addressed. A dead time of 50 ms is then initiated during which all the register data (00h ~ 18h) are stored into the non volatile EEPROM cell. During that time, there should be no data flowing through the I2C because the I2C interface is momentarily not responding.

After the 50 ms have passed, the WED bit is automatically reset to 0, and the user is able to read the values or program again.

Slave address:0100000X
X = R/WR/W = 1 → read mode
R/W = 0 → write mode
Table 11-1 Register Map
REGISTERNAMEADDRESSFACTORY
VALUE
BIT COUNTSTEPS COUNT
VDDBoost00h21h664
VCCBuck01h09h for TPS65175413
03h for TPS65175A
VGH_LTPositive charge pump - Low Temperature02h0Bh416
VGH_HTPositive charge pump - High Temperature03h0Bh416
VGLNegative charge pump04h20h664
DLY0Enable delay05h01h38
DLY1VGL delay06h01h38
DLY2VDD delay07h03h38
DLY3VGH delay08h03h38
GMA1Gamma buffer 109h01h1512
0Ah5Fh8
GMA2Gamma buffer 20Bh01h1512
0Ch06h8
GMA3Gamma buffer 30Dh00h1512
0Eh86h8
GMA4Gamma buffer 40Fh01h1512
10h86h8
GMA5Gamma buffer 511h01h1512
12h0Ch8
GMA6Gamma buffer 613h00h1512
14h9Fh8
VCOMVCOM reference15h00h1391 / 211
16hDFh8
VCOM OperationVCOM Output Range
VCOM High Temperature
VCOM Gain
17h00h8256
VCOM Temp. + Osc. Freq.VCOM Temp. Range
Oscillator Frequency
18h08h416
CRControl RegisterFFh81