SLVSBD1B December   2012  – August 2025 TPS65175

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configurations
  6. Ordering Information #GUID-A66BA10C-7D19-4133-842F-4CC0C2AD52C6/SLVSAP8211
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Thermal Information
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 I2C Interface Timing Characteristics #GUID-79B32470-0E13-4B06-925C-21E3D7AB5A31/SLVSAE57133
    6. 6.6 I2C Timing Diagrams
    7.     14
    8.     15
    9.     16
    10. 6.7 Typical Characteristics
  8. DAC Range Summary
    1.     19
    2. 7.1 Sequencing
    3. 7.2 Power-Up
    4. 7.3 Power-Down
  9. Detailed Description
    1. 8.1  Boost Converter (VDD)
      1. 8.1.1 Enable Signal (DLY2)
      2. 8.1.2 Boost Converter Operation
      3. 8.1.3 Startup (Boost Converter)
      4. 8.1.4 Protections (Boost Converter)
      5. 8.1.5 Setting the Output Voltage VDD
    2. 8.2  Boost Converter Design Procedure
      1. 8.2.1 Inductor Selection (Boost Converter)
      2. 8.2.2 Rectifier Diode Selection (Boost Converter)
      3. 8.2.3 Compensation (COMP)
      4. 8.2.4 Input Capacitor Selection
      5. 8.2.5 Output Capacitor Selection
      6. 8.2.6 DCM Mode
    3. 8.3  Buck Converter (VCC)
      1. 8.3.1 Enable Signal (UVLO)
      2. 8.3.2 Buck converter Operation
      3. 8.3.3 Startup and Short Circuit Protection (Buck Converter)
      4. 8.3.4 Setting the Output Voltage VCC
    4. 8.4  Buck Converter Design Procedure
      1. 8.4.1 Inductor Selection (Buck Converter)
      2. 8.4.2 Rectifier Diode Selection (Buck Converter)
      3. 8.4.3 Input Capacitor Selection (Buck Converter)
      4. 8.4.4 Output Capacitor Selection (Buck Converter)
      5. 8.4.5 DCM Mode
    5. 8.5  Synchronous Buck Converter (HVDD)
      1. 8.5.1 Enable Signal (DLY2)
      2. 8.5.2 Startup and Short Circuit Protection (Synchronous Buck Converter)
      3. 8.5.3 Setting the output voltage HVDD
    6. 8.6  Synchronous Buck Converter Design Procedure
      1. 8.6.1 Inductor Selection (Synchronous Buck Converter)
      2. 8.6.2 Input Capacitor Selection
      3. 8.6.3 Output Capacitor Selection
    7. 8.7  Positive Charge Pump Controller (VGH) and Temperature Compensation
      1. 8.7.1 Enable Signal (DLY3)
      2. 8.7.2 Positive Charge Pump Controller Operation
    8. 8.8  Positive Charge Pump Design Procedure
      1. 8.8.1 Diodes selection (CPP)
      2. 8.8.2 Capacitors Selection (CPP)
      3. 8.8.3 Selecting the PNP Transistor (CPP)
      4. 8.8.4 Positive Charge Pump Protection
    9. 8.9  VGH Temperature Compensation
      1. 8.9.1 Setting the output voltage VGH_LT and VGH_HT
    10. 8.10 Negative Charge Pump (VGL)
      1. 8.10.1 Enable Signal (DLY1)
      2. 8.10.2 Setting the output voltage VGL
    11. 8.11 Negative Charge Pump Design Procedure
      1. 8.11.1 Diodes Selection (CPN)
      2. 8.11.2 Capacitors selection (CPN)
      3. 8.11.3 Selecting the NPN Transistor (CPN)
      4. 8.11.4 Negative Charge Pump Protection
    12. 8.12 P-Vcom Voltage and Gain (VCOM)
      1. 8.12.1 Enable Signal (DLY2)
    13. 8.13 P-Vcom Design Procedure
      1. 8.13.1 Setting the P-Vcom gain
    14. 8.14 P-Vcom Temperature Compensation
      1. 8.14.1 Setting the VCOM output voltage
    15. 8.15 Gamma Buffer (GMA1-GMA6)
      1. 8.15.1 Enable Signal (DLY2)
      2. 8.15.2 Setting the output voltage of GMA1-GMA6
      3. 8.15.3 Output Load (Gamma Buffer)
    16. 8.16 Level Shifters
    17. 8.17 State Machine
    18. 8.18 GCLK
    19. 8.19 MCLK
    20. 8.20 GST
    21. 8.21 E/O
    22. 8.22 Reverse
    23. 8.23 VGH_F and VGH_R
    24. 8.24 VST
    25. 8.25 RESET
    26. 8.26 EVEN and ODD
    27. 8.27 Abnormal Operation
    28. 8.28 CLK1 to CLK6
    29. 8.29 Gate Voltage Shaping
    30. 8.30 Power Supply Sequencing (CLK1-CLK6, VST, RESET)
    31. 8.31 Power Supply Sequencing (EVEN, ODD)
    32. 8.32 Power Supply Sequencing (VGH_F, VGH_R)
    33.     101
    34. 8.33 Typical Applications
  10. APPENDIX – I2C INTERFACE
    1. 9.1 I2C Serial Interface Description
  11. 10Detailed Description
    1. 10.1 DAC Settings
    2. 10.2 I2C Interface Protocol
    3. 10.3 Temperature Compensation
    4. 10.4 PCB Layout Recommendations
  12. 11Register Map
  13. 12DAC Registers
  14. 13Electrostatic Discharge Caution
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Package Option Addendum
      1. 15.1.1 Packaging Information
      2. 15.1.2 Tape and Reel Information

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Packaging Information

Orderable DeviceStatus (1)Package TypePackage DrawingPinsPackage QtyEco Plan (2)Lead/Ball Finish(4)MSL Peak Temp (3)Op Temp (°C)Device Marking(5)(6)
TPS65175ARSHRACTIVEVQFNRSH563000Green (RoHS & no Sb/Br)CU NIPDAULevel-3-260C-168 HR-40 to 85TPS65175A
TPS65175RSHRACTIVEVQFNRSH563000Green (RoHS & no Sb/Br)CU NIPDAULevel-3-260C-168 HR-40 to 85TPS65175
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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