ZHCSLO0B April   2023  – October 2023 TPS62874-Q1 , TPS62875-Q1 , TPS62876-Q1 , TPS62877-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6.   Device Options
  7. 5 Pin Configuration and Functions
  8. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings - Q100
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Typical Characteristics
  9. 7 Parameter Measurement Information
  10. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed-Frequency DCS-Control Topology
      2. 8.3.2  Forced-PWM and Power-Save Modes
      3. 8.3.3  Transient Non-Synchronous Mode (optional)
      4. 8.3.4  Precise Enable
      5. 8.3.5  Start-Up
      6. 8.3.6  Switching Frequency Selection
      7. 8.3.7  Output Voltage Setting
        1. 8.3.7.1 Output Voltage Range
        2. 8.3.7.2 Output Voltage Setpoint
        3. 8.3.7.3 Non-Default Output Voltage Setpoint
        4. 8.3.7.4 Dynamic Voltage Scaling
        5. 8.3.7.5 Droop Compensation
      8. 8.3.8  Compensation (COMP)
      9. 8.3.9  Mode Selection / Clock Synchronization (MODE/SYNC)
      10. 8.3.10 Spread Spectrum Clocking (SSC)
      11. 8.3.11 Output Discharge
      12. 8.3.12 Undervoltage Lockout (UVLO)
      13. 8.3.13 Overvoltage Lockout (OVLO)
      14. 8.3.14 Overcurrent Protection
        1. 8.3.14.1 Cycle-by-Cycle Current Limiting
        2. 8.3.14.2 Hiccup Mode
        3. 8.3.14.3 Current-Limit Mode
      15. 8.3.15 Power Good (PG)
        1. 8.3.15.1 Standalone / Primary Device Behavior
        2. 8.3.15.2 Secondary Device Behavior
      16. 8.3.16 Remote Sense
      17. 8.3.17 Thermal Warning and Shutdown
      18. 8.3.18 Stacked Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Undervoltage Lockout
      3. 8.4.3 Standby
      4. 8.4.4 On
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 8.5.3 HS-Mode Protocol
      4. 8.5.4 I2C Update Sequence
      5. 8.5.5 I2C Register Reset
      6. 8.5.6 Dynamic Voltage Scaling (DVS)
    6. 8.6 Device Registers
  11. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Selecting the Input Capacitors
        3. 9.2.2.3 Selecting the Compensation Resistor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Compensation Capacitor CC
        6. 9.2.2.6 Selecting the Compensation Capacitor CC2
      3. 9.2.3 Application Curves
    3. 9.3 Application Using Two TPS62876-Q1 in a Stacked Configuration
      1. 9.3.1 Design Requirements For Two Stacked Devices
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Selecting the Compensation Resistor
        2. 9.3.2.2 Selecting the Output Capacitors
        3. 9.3.2.3 Selecting the Compensation Capacitor CC
      3. 9.3.3 Application Curves for Two Stacked Devices
    4. 9.4 Application Using Three TPS62876-Q1 in a Stacked Configuration
      1. 9.4.1 Design Requirements For Three Stacked Devices
      2. 9.4.2 Detailed Design Procedure
        1. 9.4.2.1 Selecting the Compensation Resistor
        2. 9.4.2.2 Selecting the Output Capacitors
        3. 9.4.2.3 Selecting the Compensation Capacitor CC
      3. 9.4.3 Application Curves for Three Stacked Devices
    5. 9.5 Best Design Practices
    6. 9.6 Power Supply Recommendations
    7. 9.7 Layout
      1. 9.7.1 Layout Guidelines
      2. 9.7.2 Layout Example
  12. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 静电放电警告
    5. 10.5 术语表
  13. 11Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

GUID-20220408-SS0I-ZSPZ-HFG6-5MG4RTDDJHKQ-low.svg Figure 5-1 RZV Package 24 Pin VQFN
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
1 VOSNS

I

 Output voltage sense (differential output voltage sensing).
2 EN I This pin is the enable pin of the device. Connect to this pin using a series resistor of at least 15 kΩ. A logic low level on this pin disables the device, and a logic high level on the pin enables the device. Do not leave this pin unconnected.

For stacked operation interconnect EN pins of all stacked devices with a resistor to the supply voltage or a GPIO of a processor. See Stacked Operation for a detailed description.
3 FSEL I Frequency select pin. A resistor or a short circuit to GND or VIN determines the switching frequency if not externally synchronized. See Section 8.3.6 for the frequency options.
4 VSEL I Start-up output voltage set pin. A resistor or short circuit to GND or VIN defines the selected output voltage.
5, 6, 15, 16 VIN P Power supply input. Connect the input capacitor as close as possible between pin VIN and GND.
7, 8,

13, 14

 GND GND Ground pin
9, 10, 11, 12 SW O This is the switch pin of the converter and is connected to the internal Power MOSFETs.
17 SYNCOUT O Internal clock output pin for synchronization in stacked mode. Leave this pin floating for single device operation. Connect this pin to the MODE/SYNC pin of the successing device in the daisy-chain in stacked operation. Do not use this pin to connect to a non-TPS6287x-Q1 device.

During start-up, this pin is used to identify if a device must operate as a secondary converter in stacked operation. Connect a 47-kΩ resistor from this pin to GND to define a secondary converter in stacked operation. See Stacked Operation for a detailed description.
18 MODE/SYNC I The device runs in Power-Save mode when this pin is pulled low. If the pin is pulled high, the device runs in Forced-PWM mode. Do not leave this pin unconnected. The mode pin can also be used to synchronize the device to an external clock.
19 SDA I/O I2C serial data pin. Do not leave this pin floating. Connect a pullup to logic high level.

Connect to GND for secondary devices in stacked operation.

20

 SCL I/O I2C serial clock pin. Do not leave this pin floating. Connect a pullup resistor to a logic high level.

Connect to GND for secondary devices in stacked operation.

21

 PG I/O Open drain power good output. Low impedance when not "power good", high impedance when "power good". This pin can be left open or be tied to GND when not used in single device operation.

In stacked operation interconnect the PG pins of all stacked devices. Only the PG pin of the primary converter in stacked operation is an open drain output. For devices that are defined as secondary converters in stacked mode the pin is an input pin. See Stacked Operation for a detailed description.

22

 AGND GND Analog Ground. Connect to GND.

23

 COMP – Device compensation input. A resistor and capacitor from this pin to AGND define the compensation of the control loop.

In stacked operation connect the COMP pins of all stacked devices together and connect a resistor and capacitor between the common COMP node and AGND.

24

GOSNS

I

Output ground sense (differential output voltage sensing)

Exposed Thermal Pads

 —

The thermal pads must be soldered to GND to achieve an appropriate thermal resistance and for mechanical stability.