ZHCSBB4B July   2013  – June 2017 TPS61197

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Supply Voltage
      2. 7.3.2 Boost Controller
      3. 7.3.3 Switching Frequency
      4. 7.3.4 Enable and Undervoltage Lockout
      5. 7.3.5 Power-Up Sequencing and Soft Start-up
      6. 7.3.6 Current Regulation
      7. 7.3.7 PWM Dimming
      8. 7.3.8 Indication for Fault Conditions
    4. 7.4 Device Functional Modes
      1. 7.4.1 Protections
        1. 7.4.1.1 Switch Current Limit Protection Using the ISNS Pin
        2. 7.4.1.2 LED Open Protection
        3. 7.4.1.3 Schottky Diode Open Protection
        4. 7.4.1.4 Schottky Diode Short Protection
        5. 7.4.1.5 IFB Overvoltage Protection
        6. 7.4.1.6 Output Overvoltage Protection Using the OVP Pin
        7. 7.4.1.7 IFB Short-to-Ground Protection
        8. 7.4.1.8 Thermal Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Simple Boost Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Inductor Selection
          2. 8.2.1.2.2 Output Capacitor
          3. 8.2.1.2.3 Schottky Diode
          4. 8.2.1.2.4 Switch MOSFET and Gate Driver Resistor
          5. 8.2.1.2.5 Current Sense and Current Sense Filtering
          6. 8.2.1.2.6 Loop Consideration
        3. 8.2.1.3 Application Curves
      2. 8.2.2 PWM Dimming Controlled by Boost Converter
      3. 8.2.3 High Boost Ratio Application
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.2.1.2.6 Loop Consideration

The COMP pin on the TPS61197 is used for external compensation, allowing the loop response to be optimized for each application. The COMP pin is the output of the internal trans-conductance amplifier. The external resistor R8, along with ceramic capacitors C6 (see Figure 18), are connected to the COMP pin to provide poles and zero. The pole and zero, along with the inherent pole and zero in a peak current mode control boost converter, determine the closed loop frequency response. This is important to converter stability and transient response.

The first step is to calculate the pole and the right half plane zero of the peak current mode boost converter by Equation 11 and Equation 12.

Equation 11. TPS61197 eq11_fp_lvsc25.gif
Equation 12. TPS61197 eq12_fzrhp_lvsc25.gif

To make the loop stable, the loop must have sufficient phase margin at the crossover frequency where the loop gain is 1. To avoid the effect of the right half plane zero on the loop stability, choose the crossover frequency fCO less than 1/5 of the fZRHP. Then calculate the compensation components by Equation 13 and Equation 14.

Equation 13. TPS61197 eq13_R8_lvsc25.gif

where

  • VOVPTH = 3.04 V, which is the overvoltage protection threshold at the OVP pin
  • VOUT_OVP is the setting output over-voltage protection threshold
  • GmEA is the trans-conductance of the error amplifier (the typical value of the GmEA is 120 μs)
  • fCO is the crossover frequency, which normally is less than 1/5 of the fZRHP
Equation 14. TPS61197 Eq14_C6_lvsc25.gif

where

  • fP is the pole’s frequency of the power stage calculated by Equation 11

If the output capacitor is the electrolytic capacitor which may have large ESR, a capacitor is required at the COMP pin or at the OVP pin to cancel the inherent zero of the output capacitor.