ZHCS026C December   2010  – February 2016 TPS57060-Q1

PRODUCTION DATA.  

  1. 1 特征
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化电路原理图
      2.      效率与负载电流间的关系
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Low Dropout Operation and Bootstrap Voltage (BOOT)
      4. 7.3.4  Error Amplifier
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Adjusting the Output Voltage
      7. 7.3.7  Enable and Adjusting Undervoltage Lockout (UVLO)
      8. 7.3.8  Slow Start and Tracking Pin (SS/TR)
      9. 7.3.9  Overload Recovery Circuit
      10. 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 7.3.11 Overcurrent Protection and Frequency Shift
      12. 7.3.12 Selecting the Switching Frequency
      13. 7.3.13 How to Interface to RT/CLK Pin
      14. 7.3.14 Power Good (PWRGD Pin)
      15. 7.3.15 Overvoltage Transient Protection
      16. 7.3.16 Thermal Shutdown
      17. 7.3.17 Small Signal Model for Loop Response
      18. 7.3.18 Simple Small-Signal Model for Peak Current-Mode Control
      19. 7.3.19 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sequencing
      2. 7.4.2 Pulse Skip Eco-Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting the Switching Frequency
        2. 8.2.2.2  Output Inductor Selection (LO)
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Catch Diode
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Slow Start Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Undervoltage Lockout Set Point
        9. 8.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 8.2.2.10 Compensation
        11. 8.2.2.11 Discontinuous Mode and Eco Mode Boundary
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation Estimate
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 开发支持
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.13 How to Interface to RT/CLK Pin

The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 34. The square wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin and have an on time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range is 300 kHz to 2200 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit should be designed in such a way that the device will have the default frequency set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. TI recommends to use a frequency set resistor connected as shown in Figure 34 through a 50-Ω resistor to ground. The resistor should set the switching frequency close to the external CLK frequency. TI recommends to AC couple the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin and a 4-kΩ series resistor. The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock and in applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the CLK threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5-V voltage source is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Because there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or decrease the switching frequency until the PLL locks onto the CLK frequency within 100 ms.

When the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK frequency to 150 kHz, then reapply the 0.5-V voltage and the resistor then sets the switching frequency. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 V on VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Figure 35, Figure 36 and Figure 37 show the device synchronized to an external system clock in continuous conduction mode (CCM) discontinuous conduction (DCM) and pulse skip mode (PSM).

TPS57060-Q1 syn_sys_clk_lvsap2.gifFigure 34. Synchronizing to a System Clock
TPS57060-Q1 ccm_plt_lvsa25.gifFigure 35. Plot of Synchronizing in CCM
TPS57060-Q1 skip_mod_lvsa25.gifFigure 37. Plot of Synchronizing in PSM
TPS57060-Q1 dcm_plt_lvsa25.gifFigure 36. Plot of Synchronizing in DCM