ZHCS137F March   2011  – October 2017 TPS54622

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化电路原理图
      2.      效率与负载电流间的关系
  4. 4 修订历史记录
  5. 5 Pin Configurations and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency PWM Control
      2. 7.3.2  Continuous Current Mode Operation (CCM)
      3. 7.3.3  VIN and Power VIN Pins (VIN and PVIN)
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Adjusting the Output Voltage
      6. 7.3.6  Safe Start-Up Into Prebiased Outputs
      7. 7.3.7  Error Amplifier
      8. 7.3.8  Slope Compensation
      9. 7.3.9  Enable and Adjusting Undervoltage Lockout
      10. 7.3.10 Adjustable Switching Frequency and Synchronization (RT/CLK)
      11. 7.3.11 Slow Start (SS/TR)
      12. 7.3.12 Power Good (PWRGD)
      13. 7.3.13 Output Overvoltage Protection (OVP)
      14. 7.3.14 Overcurrent Protection
        1. 7.3.14.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.14.2 Low-Side MOSFET Overcurrent Protection
      15. 7.3.15 Thermal Shutdown
      16. 7.3.16 Small Signal Model for Loop Response
      17. 7.3.17 Simple Small Signal Model for Peak Current Mode Control
      18. 7.3.18 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Adjustable Switching Frequency (RT Mode)
      2. 7.4.2 Synchronization (CLK Mode)
      3. 7.4.3 Bootstrap Voltage (BOOT) and Low Dropout Operation
      4. 7.4.4 Sequencing (SS/TR)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedures
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Operating Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  Slow-Start Capacitor Selection
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Undervoltage Lockout Setpoint
        9. 8.2.2.9  Output Voltage Feedback Resistor Selection
          1. 8.2.2.9.1 Minimum Output Voltage
        10. 8.2.2.10 Compensation Component Selection
        11. 8.2.2.11 Fast Transient Considerations
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Estimated Circuit Area
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 开发支持
      3. 11.1.3 使用 WEBENCH® 工具创建定制设计
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.17 Simple Small Signal Model for Peak Current Mode Control

Figure 21 is a simple small signal model that can be used to understand how to design the frequency compensation. The device power stage can be approximated to a voltage controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 5 and consists of a DC gain, one dominant pole and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 20) is the power stage transconductance (gmps) which is 16 A/V for the device. The DC gain of the power stage is the product of gmps and the load resistance ®L) as shown in Equation 6 with resistive loads. As the load current increases, the DC gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole moves with load current (see Equation 7). The combined effect is highlighted by the dashed line in Figure 22. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation.

TPS54622 sds_freq_resp_schem_slvsa70.gifFigure 21. Simplified Small Signal Model for Peak Current Mode Control
TPS54622 sds_freq_resp_wave_slvsa70.gifFigure 22. Simplified Frequency Response for Peak Current Mode Control
Equation 5. TPS54622 eq8_vout_lvs949.gif
Equation 6. TPS54622 eq9_adc_lvs949.gif
Equation 7. TPS54622 eq10_fp_lvs949.gif
Equation 8. TPS54622 eq11_fz_lvs949.gif

where

gmps is the power stage gain (16 A/V).

RL is the load resistance.

CO is the output capacitance.

RESR is the equivalent series resistance of the output capacitor.